S7-200 Periodic Pulse Output: Timer Setup and PWM Methods

1. Problem Definition and Functional Requirements

The classic S7-200 periodic-pulse problem is small enough to be ignored in textbooks and large enough to expose a number of platform-specific gotchas. The functional specification is: a CPU in the SIMATIC S7-200 family must issue a fixed 4-second output pulse repeatedly. The repetition period is selected by two binary inputs (four possible periods), and a third binary input acts as a master inhibit. The pulse must be repeatable, deterministic, and survive the inevitable edge case where the inhibit arrives mid-pulse.

Decoupling the requirement into primitives gives the engineer a checklist before any code is written:

• Pulse width: 4.000 s, fixed, no modulation required.
• Pulse repetition period: 1 of 4 values, selected by inputs I_x and I_y.
• Master inhibit: I_z = 0 freezes the output and prevents a new pulse from starting. I_z = 1 allows the cycle to run.
• Behavior at inhibit-true mid-pulse: the specification should explicitly state whether the active 4 s pulse is allowed to complete or must be truncated. Both behaviors are easy to implement; the difference is whether the reset path of the pulse timer is gated by I_z.
• Behavior when period-select inputs change while running: the implementation must decide between immediate update (re-loads the period) and update-on-next-cycle (the change takes effect after the current period expires).

2. S7-200 Hardware Platform Selection

The S7-200 label covers two distinct hardware generations. Choosing the correct CPU determines which instruction set, time bases, and PWM channels are available.

The 22x generation is recommended for any new machine. The 21x series has been obsolete for over a decade and a half and is no longer supported with firmware updates or new STEP 7 Micro/WIN project files. Field-replacement must use the 22x or the modern S7-200 SMART (which uses a different instruction set and is not binary-compatible).

3. Timer Fundamentals on the S7-200

Unlike a Siemens S5 or S7-300/400, the S7-200 does not let the programmer pick a time base per timer. The time base is fixed by the timer number, not by a parameter. Engineers who learned ladder on the S5 consistently trip over this.

Key constraints that drive the implementation:

• The PT (preset) value of a timer is a 16-bit signed integer. The maximum value is 32 767, which combined with the resolution gives the maximum interval per row above.
• The PT input is normally a constant, but the S7-200 permits a variable PT connected to a VW (variable word) or MW (marker word). This is the only practical way to change the period from inputs at runtime.
• The ET (elapsed time) is updated by the scan cycle. On a 1 ms resolution timer, the actual bit transition is decoded inside the CPU and reflected in the next scan, so a 4 s pulse driven by a T37 (100 ms) has a worst-case 100 ms jitter relative to the requested edge.
• A self-resetting timer (a TON whose enable contact is its own NC bit) introduces additional rules. The section on self-resetting timers below covers them in detail because they are the single most common source of subtle bug reports on the S7-200.

4. Method A — Standard Timer with Variable PT

This is the method that maps most cleanly onto the question: a TON with a variable PT selected by two binary inputs, plus a master inhibit. It works on every CPU from the 214 onward.

4.1 Memory map

4.2 Period-preset table

Two inputs give four codes. Pick four real periods that suit the application, multiply by 10 to get 100 ms counts, and load them into four VW constants. The example uses 10 s, 30 s, 60 s, 120 s.

4.3 Network-by-network ladder

Write this in STEP 7 Micro/WIN V4.0 SP9 or later. Micro/WIN stores projects as .mwp and exports to .awl for offline review.

1. Network 1 — period select via four MOV_W instructions. Use I0.0 and I0.1 as contacts in series for each branch, then a MOVW of the constant into VW200. The four branches load 100, 300, 600, or 1200 depending on the input code. Leave the rung un-conditional so the period is updated on every scan; the variable will simply be rewritten with the same value if the inputs do not change.
2. Network 2 — master inhibit and run latch. SET M0.0 on the rising edge of I0.2 (use EU, edge-up). RESET M0.0 on the falling edge of I0.2 (use ED, edge-down). This gives a clean enable flag rather than tracking a level.
3. Network 3 — pulse timer T37. IN = M0.0 AND NOT Q0.0 (the latter prevents re-trigger while a pulse is already in progress). PT = 40 (4 s × 10 ticks). When T37 reaches 4 s, it sets Q0.0 directly through its own contact if you drive Q0.0 from T37's bit, or, more cleanly, with a SET/RESET on Q0.0 gated by the T37 contact.
4. Network 4 — period timer T38. IN = M0.0. PT = VW200. When T38 done, it resets M0.0 and Q0.0. On the next scan, M0.0 is re-asserted by the edge of I0.2 (which is still high) and the cycle restarts.

4.4 The self-resetting timer caveat

When a TON's enable contact is the timer's own NC contact, the S7-200 update mechanism in firmware versions prior to REL_22 deviates from the IEC 61131-3 model by one scan: the bit transition is latched at the start of the next scan, not at the moment the elapsed time crosses the preset. Three rules avoid the bug:

1. Do not place a 1 ms timer (T32, T96, T0, T64) in a self-resetting path. Use a 10 ms or 100 ms timer so the bit-decoding latency is at most one tick of the resolution you are counting.
2. Use a separate DONE bit (a marker or Q output) and reset the timer explicitly from that bit in the next network, rather than relying on a NC contact on the timer bit to break the IN path.
3. Verify on the bench with a stopwatch that the actual pulse width matches PT × resolution to within one resolution tick. If you see 4.1 s when you asked for 4.0 s, the timer is in self-reset mode and you have the firmware-bug variant.

5. Method B — PWM Output Subsystem

The S7-200's PWM output is a hardware peripheral, not a ladder construct. It runs in the background and continues to produce the configured waveform regardless of scan time, which makes it the correct choice for any pulse output that must be jitter-free or that runs faster than 100 ms.

5.1 PWM specification

On a CPU 224, the two PWM channels are Q0.0 (PWM0) and Q0.1 (PWM1). On a CPU 224XP, the high-speed PWM on Q0.3 is configured by the same PLS instruction but accepts PTO mode as well.

5.2 Configuring PWM0 with the PLS instruction

PWM is set up by writing a control byte (SMB67 for PWM0, SMB77 for PWM1) and then loading cycle and pulse-width words (SMW68 / SMW70) before issuing PLS. The control byte selects microsecond vs millisecond mode, whether the time base is updated, and whether the output runs continuously or for a fixed pulse count.

Network 1 — one-shot initialization on first scan
      SM0.1                MOVB   16#C1, SMB67   // 1100 0001: enable PWM0, ms mode, continuous
      |                    MOVW   +1000, SMW68   // 1 s cycle
      |                    MOVW   +4000, SMW70   // 4 s pulse width (40 % duty)
      |                    PLS    0              // write configuration to PWM0

Network 2 — inhibit via PWM enable bit in SMB67
      I_inhibit (I0.2)      MOVB   16#C1, SMB67   // bit 7 = 1, PWM0 active
      |                     PLS    0
      NOT I_inhibit         MOVB   16#41, SMB67   // bit 7 = 0, PWM0 gated off
      |                     PLS    0

Setting bit 7 of SMB67 to 0 freezes the waveform at its current level. Setting it to 1 resumes the waveform from the last cycle edge. The transition is not glitch-free; if a deterministic phase relationship to the inhibit input is required, gate the Q0.0 output with an external relay or use the inhibit to load a 0-pulse-width value (output held low) instead of disabling PWM0 entirely.

5.3 Variable period with PWM

Because the cycle and pulse-width words are writable at any time, a period-select network identical to the one in Method A can load SMW68 (cycle) and SMW70 (pulse width) from a lookup, then re-issue PLS to apply. The change takes effect at the next cycle boundary, so the new period is phase-coherent rather than abrupt.

6. SMO and SMB Special Memory Bits for Pulse Generation

The S7-200 exposes a number of fixed-frequency clock bits that can simplify the period-select logic or drive a base timebase. The relevant bits for pulse work are:

SM0.5 in combination with a counter gives a 4 s pulse without any explicit TON: count four rising edges, set the output, count four more, reset. The counter is the CTU with C0..C255. Preset the counter to 4, the 1 s clock gives the resolution, and the output is a clean 4 s pulse on every fourth second.

7. Inhibit Logic and Edge-Case Behaviour

The question of what happens when the inhibit arrives mid-pulse is the only place this application can have a hidden trap. There are three valid behaviours, each with a different implementation:

Document the chosen behaviour in the I/O list. Field commissioning goes wrong most often when the customer and the integrator have different mental models of the abort case.

8. State-Machine View

For documentation and for HMI display, a four-state machine captures every transition cleanly:

The diagram is a documentation aid only; the ladder logic does not need an explicit state register on a CPU 224, where the M0.x and timer bits serve the same role.

9. STEP 7 Micro/WIN Project Setup

1. Launch STEP 7 Micro/WIN. Confirm the project is set to the correct CPU type under CPU > Type. The wrong CPU type is the most common reason for an apparently correct program to refuse to download.
2. Open Tools > Options > STL/Micro/WIN and enable instruction tree view; the PLS, TON, CTU, and MOVW blocks are all in the Instructions tree.
3. Use the Symbol Table to assign every address (I0.0, M0.0, T37, VW200) a meaningful name. The project becomes searchable and the cross-reference (Ctrl+F3) jumps directly to the rung.
4. Compile with Ctrl+B. A clean compile with zero errors is required before download. Warnings about duplicate coil assignments or unreachable rungs are a hint that the timer and inhibit logic have a race condition.
5. Download with the PC/PPI cable (RS-485) or, on 22x CPUs, an Ethernet CP 243-1 module if installed. Set the PPI address to 2 (the S7-200 default) and the baud to 9.6 kbps for legacy 21x or 187.5 kbps for 22x.
6. Switch to Online > Monitor (Ctrl+M). Watch T37, T38, VW200, and Q0.0 in real time. Trigger the inputs from the Status Chart to validate the full matrix.

10. Verification and Commissioning Procedure

For a PWM-based implementation, repeat steps 1–7 with a 100 MHz oscilloscope on Q0.0. Verify that the cycle time matches the loaded value within ±1 µs and that the pulse width is exactly 4 s within the configured resolution.

11. Troubleshooting Matrix

12. Migration to S7-200 SMART and S7-1200

If the machine is being re-engineered rather than maintained, two paths exist:

• S7-200 SMART (CPU SR20 / ST40 / SR60): drop-in replacement for 22x projects. The S7-200 SMART keeps the same instruction set but uses STEP 7 Micro/WIN SMART, adds Ethernet, and supports the same PWM and PTO/PWM peripherals on Q0.0 and Q0.1. The migration tool in Micro/WIN SMART imports the .mwp file and flags incompatible instructions.
• S7-1200 (CPU 1211C through 1215C): a new project in TIA Portal. The 4 s pulse with variable period collapses into one or two IEC timers with a wider resolution (1 ms default) and the PWM is configured in the device configuration rather than via SMB control bytes.

For brand-new design work, do not start on the S7-200. The platform is in mature maintenance, the documentation set is frozen, and the engineering community is shrinking. Start on the S7-1200 or S7-1500 and treat any S7-200 work as a sustaining-engineering task.

13. Field-Notes Caveats

• The 21x CPU does not have an EEPROM for the program; battery-backed RAM is the only persistence. If the battery dies, the program is lost and the CPU starts in a stopped state. The 22x has an integrated EEPROM and survives a dead battery.
• The PPI cable's RS-485 transceiver is 5 V tolerant on the S7-200 side but not on every laptop. Use a USB/PPI or USB/MPI cable with isolation; the un-isolated variant is a known cause of laptop RS-232 port failures.
• Micro/WIN V4.0 SP9 is the last version that supports the 21x series. If you are on SP5 or earlier and a customer is on a 215, update to SP9 before doing more than a status-chart read.
• Wiring a relay or solenoid to Q0.0 without a snubber diode across the coil will inject 50–200 V transients on every pulse edge. The 22x outputs are not optoisolated, and repeated transients have been known to damage the high-side driver. Always add a 1N4007 (DC) or MOV (AC) across the coil.