S7-300 CPU 313C ±10V Analog Output for VFD Motor Direction

1. Overview

This reference covers programming a Siemens SIMATIC S7-300 (CPU 313C, 6ES7 313-5BF03-0AB0 or later) analog output channel to produce a bipolar ±10 VDC reference that commands a Parker variable frequency drive (VFD) for bidirectional motor operation. The objective is to eliminate the conventional discrete forward/reverse input wiring and use only the polarity of the analog reference to set motor direction: 0 V = stop, +10 V = maximum speed forward, -10 V = maximum speed reverse.

The integration is anchored in three engineering decisions: (1) which physical output channel carries the reference, (2) how the signed 16-bit integer at the peripheral output word (in this case PQW750) maps to voltage, and (3) how the VFD is parameterized to interpret a bipolar signal as both speed and direction. Each is treated in detail below, with code in STEP 7 (LAD/STL) and TIA Portal (SCL), wiring guidance, Parker VFD parameter maps, a bipolar-mode cross-reference to the Allen-Bradley PowerFlex 40/525, and a troubleshooting matrix for the most common field faults.

2. Prerequisites

1. STEP 7 V5.5+ or TIA Portal V13+ with the CPU 313C HSP or GSD/GML file installed.
2. Hardware configuration matching the physical rack: CPU 313C in slot 2, SM 332 in the slot that yields PQW750 in the address overview.
3. Parker VFD with an analog input rated for ±10 V bipolar (or a programmable bipolar mode). Verify against the drive's parameter manual — older 0–10 V-only drives will read the negative half-scale as a fault.
4. Shielded twisted-pair cable (Belden 8760 or equivalent) for the analog run, terminated at both ends to a clean low-impedance ground.
5. Wiring tools: 4 mm ferrules, torque driver calibrated to the SM 332 front connector (0.5–0.8 N·m).
6. Multimeter with true RMS and a calibrated loop calibrator to verify 0.000 V, +10.000 V, and -10.000 V at the drive terminals before enabling run.

3. CPU 313C and SM 332 Hardware Reference

The CPU 313C itself does not include analog outputs. The signal at PQW750 is sourced from a 6ES7 332-x analog output module configured in STEP 7 Hardware (HW Config) for bipolar voltage output. The most common selections are:

The output range is selected per-channel in HW Config under "Output type -> Voltage / Bipolar". Selecting bipolar forces the integer scaling to span the full -27648 … +27648 range; selecting unipolar clips negative values to 0 V at the output stage.

4. Bipolar ±10 V Signal Theory

A bipolar analog reference uses the polarity of the signal as a command. Three electrical landmarks are critical:

The integer-to-voltage transfer function is linear across the entire bipolar span. The general formula:

V_OUT [V] = (INTEGER / 27648) × 10

The reverse for converting a desired engineering value (e.g., percent speed or Hz) to integer:

INTEGER = (V_OUT / 10) × 27648 = PERCENT × 276.48

Engineering conversion to Hz (assuming a 50 Hz maximum):

INTEGER = (Hz_DESIRED / Hz_MAX) × 27648 × DIR

where DIR = +1 for forward, -1 for reverse, and 0 for stop. Any value between -10 V and +10 V is a valid speed command, including the dead-band the VFD applies internally for the stop window (typically ±0.5 V).

5. Identifying the Real Address of PQW750

The numeric value PQW750 is a peripheral output word address. The actual byte layout in STEP 7 increments by 2 for each analog output (16-bit word) of each configured module. To verify or correct the address:

1. Open the S7 project in STEP 7.
2. Double-click the SM 332 in the rack to open the object properties.
3. Switch to the "Addresses" tab.
4. Note the starting address of the output range, then add 2 for each channel offset (channel 0 = base, channel 1 = base + 2, etc.).
5. If the address shown is not PQW750, either correct the program's symbolic references or move the module to a different slot to match the user's existing logic.

6. Wiring the SM 332 to the Parker VFD

The SM 332 voltage outputs are differential (Vout+ and Vout-) with a common-mode return on the S- terminal. Parker VFDs with a bipolar-compatible analog input card typically expose a terminal pair marked AI+, AI-, and a 0V / COM reference.

Wiring procedure:

1. Strip the analog cable shield back 25 mm; twist the drain wire into a pigtail and bond it to the cabinet PE bar at the S7-300 end only.
2. Land Vout+ on AI+, Vout- on AI-, and M on 0V/COM at the VFD.
3. Set the VFD's analog input jumper (if present) to "Voltage" — not "Current" — and the range to "±10 V" or "Bipolar 10 V" depending on model.
4. Torque the front connector screws to 0.6 N·m. Re-torque after 24 hours of thermal cycling.

7. Parker VFD Configuration for Bipolar Reference

The exact parameter labels vary by Parker family. The following map applies to the most common industrial models (AC10, AC20, AC30, SSD 650V, Compax3). Refer to the specific Parker drive manual for the parameter numbers native to your firmware version.

8. STEP 7 (LAD / STL) Programming

8.1 Direct write of a constant

Minimum-viable block: load a signed integer into the output word. Use the INT data type so that negative values pass through the accumulators correctly.

// STL, OB1, network 1
L     13824              // 50 % forward (+5 V)
T     PQW 750            // write to SM 332 channel

// Negative example (50 % reverse)
L     -13824             // -5 V
T     PQW 750

8.2 Scaling from a percent setpoint (LAD)

Use a MUL (multiplier) and store the result. Avoid REAL conversions unless you implement a full FC with the IEC standard scale block (FC105). For a direct scale, integer multiplication is sufficient when the setpoint is in tenths of a percent.

// LAD, OB1 network 2
//  |    DB1.DBW0  -->  MW100 (setpoint, units: 0.1 % signed, -1000..+1000)
//  |    L  +276     // 276.48 × 10 = 2765 for 100 % = 27648
//  |    *I         // MW100 * 276 / 10 (use MUL for INT)
//  |    T  MW102
//  |    L  10
//  |    /I         // divide for tenths-of-percent scaling
//  |    T  PQW 750

8.3 Scaling with engineering units in Hz

For drives parameterized in Hz, with a 50 Hz maximum, scale a 0.1-Hz-resolution INT (-500..+500):

// STL, OB1 network 3
L     DB1.DBW10          // user setpoint, units of 0.1 Hz, INT, signed
L     276               // 27648 / 100 = 276.48
*D
T     MD110             // DINT intermediate (avoid INT overflow)
L     100
/D
T     PQW 750

For a 60 Hz maximum, replace the constants with 230 (i.e., 23040 / 100) — or better, use a configurable limit stored in a data block to avoid hard-coded ratios.

9. TIA Portal (SCL) Programming

The equivalent SCL block is the recommended modern approach. It uses the IEC 61131-3 NORM_X / SCALE_X standard functions for portability.

// FB "VfdBipolarCtrl", written in SCL for S7-300 in TIA Portal
// Inputs:
//   i_bEnable  : BOOL  // run permissive
//   i_rSpeedHz : REAL  // signed, in Hz (e.g. -50.0..+50.0)
//   i_rMaxHz   : REAL  // configured drive maximum (e.g. 50.0)
//   i_bStop    : BOOL  // hardware E-stop / fast stop
// Output:
//   q_wRawOut  : WORD  // wire to PQW750 in OB1
//   q_bFault   : BOOL  // overspeed / wiring check

#i_rMaxHz := LIMIT(0.1, i_rMaxHz, 600.0);

IF NOT i_bEnable OR i_bStop THEN
    q_wRawOut := 16#0000;        // 0 V
    q_bFault  := FALSE;
    RETURN;
END_IF;

IF ABS(i_rSpeedHz) > i_rMaxHz THEN
    q_bFault := TRUE;            // clamp & flag
    i_rSpeedHz := LIMIT(-i_rMaxHz, i_rSpeedHz, i_rMaxHz);
ELSE
    q_bFault := FALSE;
END_IF;

// scale to 0..27648 (unsigned) then offset to ±27648
#rScaled := (i_rSpeedHz / i_rMaxHz) * 27648.0;

#iInt := REAL_TO_INT(#rScaled);
#iInt := LIMIT(-27648, #iInt, 27648);

q_wRawOut := INT_TO_WORD(#iInt);

Call the FB in OB1 and wire the output to %QW750. The limit checks enforce the 27648 clamp even if the user setpoint is in error.

10. Direction Control Without a Digital Input

True direction-by-polarity requires three conditions on the VFD side:

1. Bipolar reference enabled. The drive must accept negative voltage at the analog input without raising a "4–20 mA loss" or "analog input under-range" fault.
2. Direction source = analog polarity. In Parker AC20 for example, parameter P-20 = "Speed + direction" — this binds direction to the sign of the reference.
3. Run permissive separate from direction. The hardware run input (terminal EN, RUN, or FWD/REV select) remains wired and is used only to enable the drive; direction follows the analog sign.

Cross-reference for the equivalent behavior in Allen-Bradley drives: the PowerFlex 40 and PowerFlex 525 support a bipolar analog mode where speed reference polarity determines direction. The drive must have the run input closed (or be in auto-run mode with stop permissive logic), and parameter 089 (PF40) or parameter 090 (PF525) is set to enable bipolar operation. The full procedure is documented in Rockwell Automation Knowledgebase Answer 26185. Although the parameter numbering is Rockwell-specific, the architectural pattern — bipolar analog reference, separate run enable, direction derived from polarity — is identical to the Parker implementation covered here and is a useful cross-platform validation reference.

11. State Machine for Stop / Forward / Reverse

A safe state machine is recommended when driving a bipolar reference because polarity alone is not fail-safe. The PLC must enforce a stop command on loss of run permissive and on communication loss:

12. Commissioning Procedure

1. Wire check. With the S7-300 in STOP, measure the Vout+ to Vout- resistance at the drive terminals. For ±10 V output stage the source impedance is <1 Ω; an open circuit or short to PE indicates a wiring fault.
2. Static voltage test. Force PQW750 = 0 online. Verify 0.000 V ±20 mV at the VFD terminals.
3. Positive scale test. Force PQW750 = 27648. Verify +9.980 V to +10.020 V at the VFD terminals. If the reading is clipped at +5 V, the output range is set to unipolar in HW Config — reconfigure to bipolar.
4. Negative scale test. Force PQW750 = -27648. Verify -9.980 V to -10.020 V. If the drive raises "AI under-range", it is configured for 0–10 V — re-enter the bipolar mode parameter on the drive.
5. Polarity test. Force PQW750 = 13824. The drive should display ~50 % forward speed and rotate forward when the run input is closed. Force PQW750 = -13824 and verify reverse rotation. Direction must flip with polarity.
6. Ramp verification. Use the VFD's keypad to confirm the configured acceleration and deceleration ramps apply equally to forward and reverse. If not, the drive's ramp parameter is direction-dependent — set a single ramp set used for both polarities.
7. Loss-of-signal test. Open the field wiring to the drive. A correctly configured Parker drive in bipolar mode should coast to stop (analog loss = 0 V). A drive configured for 4–20 mA with hardware loss detection will fault. Verify which behavior the application requires.
8. End-to-end PLC test. Run the program, ramp the setpoint from 0 to 50 Hz forward, then to 0, then to 50 Hz reverse, then to 0. Log the output of PQW750 and the drive's reported output frequency to a data block for trend analysis.

13. Troubleshooting Matrix

14. Safety Considerations

• The bipolar reference is a single point of failure. The PLC must always force PQW750 = 0 on CPU STOP, PROFIBUS/PROFINET loss, E-stop, or watchdog timeout. Use OB82 / OB86 / OB122 to set the output to zero on fault.
• Mechanical rotation in the wrong direction is a hazard. Include a digital direction-confirmation input from a sensor (e.g., back-EMF monitor, encoder, or a centrifugal switch for unidirectional-only applications) and interlock the run permissive against it.
• Deceleration energy on a hard stop from full reverse to 0 V is returned to the drive DC bus. Verify the VFD has a braking resistor sized for the worst-case stopping energy or configure a controlled ramp time long enough to keep the bus under the trip threshold.
• Avoid using the bipolar reference for emergency stop. The VFD's controlled deceleration ramps will still be applied. Use the hardware E-stop input (Safe Torque Off on modern drives) for category 1 stops.
• Galvanic isolation between the PLC and the VFD is recommended. If the VFD analog input is non-isolated, install a 1:1 signal isolator (e.g., Phoenix Contact MINI MCR) to break ground loops that can damage the SM 332 output stage.

15. Verification Checklist

• [ ] SM 332 output range set to bipolar ±10 V in HW Config
• [ ] Address PQW750 matches the slot-loaded module
• [ ] PQW750 = 0 → 0.000 V at VFD terminals
• [ ] PQW750 = +27648 → +10.000 V at VFD terminals
• [ ] PQW750 = -27648 → -10.000 V at VFD terminals
• [ ] VFD configured for bipolar analog input
• [ ] VFD direction source = analog polarity
• [ ] Acceleration / deceleration ramps apply to both polarities
• [ ] PLC forces PQW750 = 0 on CPU STOP and fieldbus loss
• [ ] Mechanical rotation direction verified against signage convention