S7-300 FC106 UNSCALE: Converting REAL Values to 8/12/16-bit Analog Outputs

FC106 (UNSCALE) is the inverse of FC105 (SCALE). It accepts a floating-point (REAL) engineering value at its input and produces an integer that is compatible with the S7-300 analog I/O representation (0 to 27648 nominal full-scale). This reference explains how FC106 behaves on 8-bit, 12-bit, and 16-bit analog modules, and how to drive a module with less than 16 bits of resolution without modifying the FC106 call.

The companion Siemens application note Scaling and Unscaling Analog Values documents both FC105 and FC106 in STEP 7 V5.x and is the canonical source for the parameter list, transfer function, and the bipolar/unipolar behavior described below.

1. Overview of FC106 (UNSCALE)

FC106 is delivered as part of the STEP 7 Standard Library under Standard Library > PID Control Blocks. It is a standard function, not a system function (SFC/SFB), and is replicated into the project S7 program container at the time the library is opened and the block is dragged into a code block. The block number is fixed at FC106 and the instance DB is not used.

Function transfer equation (unipolar):

OUT = ( (IN - LO_LIM) / (HI_LIM - LO_LIM) ) * 27648.0

Function transfer equation (bipolar, BIPOLAR = 1):

OUT = ( (IN - LO_LIM) / (HI_LIM - LO_LIM) ) * 27648.0 - 27648.0

The integer output word is then written to the peripheral output word (PQW) of the analog output channel. The peripheral driver inside the analog module (SM332, SM334, SM335) ignores the unused low-order bits automatically when the module resolution is below 16 bits.

2. FC106 Parameter Interface

FC106 has the following formal parameters. Data types are taken from the Siemens scaling application note and the STEP 7 Online Help for FC105/FC106.

Parameter	Declaration	Data Type	Description
IN	INPUT	REAL	Engineering value to be converted (e.g. °C, bar, %)
HI_LIM	INPUT	REAL	Upper engineering limit (maps to 27648)
LO_LIM	INPUT	REAL	Lower engineering limit (maps to 0 unipolar, -27648 bipolar)
BIPOLAR	INPUT	BOOL	0 = unipolar (0…27648), 1 = bipolar (-27648…+27648)
RET_VAL	OUTPUT	WORD	FC106 return value, see error table below
OUT	OUTPUT	INT	Scaled integer suitable for PQW

The return value is a WORD, not a BOOL. A return of W#16#0000 means the operation was successful and the output lies within the supported range. A non-zero return indicates the value was clipped or an invalid input was applied.

2.1 FC106 RET_VAL Error Codes

RET_VAL (hex)	Meaning
W#16#0000	No error
W#16#0008	OUT > 27648 (unipolar) or OUT < -27648 (bipolar); output clipped to full scale
W#16#0100	OUT < 0 (unipolar only); output clipped to 0
W#16#0107	IN is not a valid REAL (NaN) or HI_LIM ≤ LO_LIM; output unchanged

3. S7-300 Analog Value Representation

Every S7-300 analog channel — input or output — exposes a 16-bit signed integer to the CPU, regardless of the actual converter resolution. The full nominal range is 0 to +27648 (unipolar) or -27648 to +27648 (bipolar). This 27648 figure is the standard Siemens convention and is used uniformly by FC105, FC106, the PID block FB41 (CONT_C), and the curve blocks FB100–FB113.

The 27648 limit is 6.25% below the theoretical 16-bit signed maximum of 32767. Siemens reserves the overrange headroom of 32768…27649 (negative overrange) and 27649…32767 (positive overrange) for diagnostics and the 0x7FFF overflow marker used by the module firmware.

3.1 Left-Justified Encoding for Sub-16-bit Modules

For analog modules with a converter resolution below 16 bits, the value is stored left-justified in the 16-bit process image. The least significant bits that are not implemented by the converter are returned as zero. The same is true on the output side: a write to PQW that sets only the upper N bits is sufficient to drive a module with N bits of D/A resolution.

Quoting the Siemens S7-300 Module Data manual: "If the resolution of an analog module has fewer than 16 bits, the analog value is stored left-justified on the module. The lower-order bit positions not used are padded with zeros." This is why FC105 and FC106 can be used universally without code modification for 8-bit, 12-bit, 14-bit, and 16-bit modules.

4. Resolution to Bit-Weighting Map

The integer at PQW is always a 16-bit left-justified word. The number of significant bits defines the LSB step size in engineering units.

Module Resolution	Significant Bits	Effective Counts	Output Range (0–10 V)	LSB Step
8 bits	8	0…255 × 256 = 0…65280 (only top 8 bits driven)	0…10 V via 256 codes	~39.1 mV / count
12 bits	12	0…4095 × 16 = 0…65520	0…10 V via 4096 codes	~2.44 mV / count
14 bits	14	0…16383 × 4 = 0…65532	0…10 V via 16384 codes	~0.61 mV / count
16 bits	16	0…65535 (Siemens uses 0…27648)	0…10 V via 27649 codes	~0.36 mV / count

The module converts the upper N bits to the analog voltage; the lower (16-N) zero bits do not change the output. The output voltage is given by:

V_out = V_fullscale * ( D / (2^N - 1) )

where D is the integer loaded into the top N bits of PQW and N is the converter resolution.

5. Why an 8-bit Output Still Reaches 10 V at FC106 Full Scale

When FC106 drives an 8-bit output module with full-scale engineering range, the following sequence occurs:

1. IN = HI_LIM → OUT is computed to 27648 (0x6C00).
2. OUT is written to PQW. Bit pattern 0x6C00 in 16-bit binary is 0110 1100 0000 0000.
3. The 8-bit DAC inside the SM334 reads the upper 8 bits = 0x6C = 108 decimal.
4. The DAC output stage maps code 108 of 255 to V_out = 10 V × (108 / 255) = 4.235 V, not 10 V.

This is the symptom reported in the field report. The root cause is a mismatch between the engineering range passed to FC106 and the actual converter resolution. The FC106 output of 27648 is not the issue; the issue is the upper 8 bits of 0x6C00 do not equal 0xFF, so the 8-bit DAC never reaches full-scale.

5.1 Rescaling the Engineering Range to Match 8-bit Counts

To make the engineering value map to 0…10 V on an 8-bit module, set HI_LIM to the engineering value that should correspond to the 8-bit full-scale of 255. Because the 8-bit DAC is left-justified, you can either:

• Option A — keep FC106 at 0…27648 and let the upper 8 bits drive the DAC, accepting that the last 6.25% of engineering range is lost (HI_LIM_real = HI_LIM × (255/256)).
• Option B — set HI_LIM so the FC106 output reaches 0xFF00 at the desired engineering end value, which is 65280 = 255 × 256.
• Option C — bypass FC106 and use a custom linearization with HI_LIM tied to the physical 8-bit count (0…255).

The cleanest engineering solution is Option C: use FC106 with the engineering range that matches the 8-bit output span directly, and let the module driver left-justify the value. For example, for a 0…100 % valve on an 8-bit output:

CALL FC 106
  IN     := MD100      // REAL percentage 0.0 ... 100.0
  HI_LIM := 1.024e+002 // 102.4 % (overshoot headroom = 2.4%)
  LO_LIM := 0.0
  BIPOLAR:= FALSE
  RET_VAL:= MW110
  OUT    := PQW 288

With HI_LIM = 102.4, an IN of 100.0 yields OUT = 0xFB00, whose upper 8 bits = 0xFB = 251, and the DAC produces 9.84 V. This headroom of 2.4% allows the loop to reach 100% cleanly.

6. STL Implementation Without FC106

If FC106 is unavailable or a more compact block is preferred, the same unscale can be coded inline in STL. The following routine mirrors FC106 unipolar behavior with bipolar support and returns a status word.

// Unscale REAL in MD100 to INT in MW110
// HI_LIM = MD104, LO_LIM = MD108, BIPOLAR = M120.0
L     MD100                  // IN
L     MD108                  // LO_LIM
-R
L     MD104                  // HI_LIM
L     MD108                  // LO_LIM
-R
/R
L     2.764800e+004
*R
JC    _ERR                   // overflow if BIAS = 0
// Bipolar offset
A     M 120.0                // BIPOLAR
JCN   _UNIP
L     2.764800e+004
-N
_UNIP: T     MW110
_OVF: SET
      SAVE
      CLR
      =     M 122.0           // RET_VAL.OK
      BEA
_ERR: L     0
      T     MW110
      SET
      =     M 122.1           // RET_VAL.OVERFLOW
      BE

7. Verification Procedure

Use the following commissioning sequence to validate the FC106 path on a real S7-300 station.

1. In STEP 7 HW Config, open the analog output module (e.g. 6ES7332-5HF00-0AB0) and confirm the output type and range match the FC106 LO_LIM/HI_LIM convention.
2. Force IN = LO_LIM via a VAT or watch table. Read PQW; expect 0x0000 on the output module channel. Measure the analog terminal with a DMM; expect 0 V (unipolar) or -10 V (bipolar).
3. Force IN = HI_LIM. Expect PQW = 0x6C00 on a 16-bit module. On an 8-bit module, expect PQW to update but the analog voltage to be limited by the converter span (see Section 5).
4. Force IN = (HI_LIM + LO_LIM) / 2. Confirm PQW = 0x3600 (mid-scale) and DMM reads 5 V on a 0…10 V range.
5. Force IN slightly above HI_LIM. Confirm RET_VAL = W#16#0008 and the output clamps at full-scale (no wrap-around).
6. Test bipolar: force IN to a negative value with BIPOLAR = 1. Confirm the output word carries 1 in bit 15 (negative integer) and the analog terminal reads the corresponding negative voltage.
7. Disconnect the field wiring and apply a test ramp from 0% to 100% at 1% steps. Plot the resulting voltage against the expected curve; deviation should be within the module's accuracy class (typically ±0.5% of full scale for SM332).

8. Common Pitfalls

• HI_LIM and LO_LIM are REAL inputs. Passing integer literals (e.g. 100) is auto-promoted by STEP 7 but will be interpreted as 100.0, not 100.0e0. Always load REAL values from MD/DBD or use the format 1.024e+002 to avoid silent truncation in older STEP 7 versions.
• BIPOLAR toggle on a unipolar module. If the module is wired for 0…10 V but BIPOLAR = 1, the FC106 will drive negative values to the PQW; the module interprets them as large positive counts and saturates at +10 V. Always set BIPOLAR = 0 for 0…10 V or 4…20 mA unipolar outputs.
• Retaining FC106 on a 12/14/16-bit upgrade. When a project is migrated from an 8-bit SM334 to a 12-bit SM332, no FC106 changes are required. The block continues to scale to 27648; the new module just uses more of the lower bits.
• Overflow flag handling. RET_VAL = W#16#0008 does not stop program execution. The PLC code must check RET_VAL before using OUT in a safety-relevant path. A typical pattern is to latch an "Analog Output Clamped" bit for HMI annunciation.
• STEP 7 V5 vs TIA Portal. FC106 exists in the Standard Library under both STEP 7 V5.x and the TIA Portal PID Compact library. The interface is identical. In TIA Portal V13, a compile error "Block FC106 has no valid version" indicates the library version shipped with the project is older than the TIA Portal version. Re-import the library from Siemens Industry Online Support.

9. S7-300 SM334 Specific Notes

The SM334 (e.g. 6ES7334-0CE01-0AA0, 6ES7334-0HE00-0AE0) is the analog combo module most commonly cited in the field report. Key constraints:

• Resolution is 8 bits for both inputs and outputs (older revisions) or 12 bits (newer 0HE00 revision).
• Two input channels and two output channels share a single converter on the 0CE01 variant; channel switching time is on the order of 5 ms per channel.
• The output range is fixed to 0…10 V; no current output is available on the 0CE01. The 0HE00 supports ±10 V, 0…10 V, and 0…20 mA depending on the wiring.
• The process image update is performed in the analog module firmware; the CPU only sees the 16-bit left-justified word.

For the 8-bit SM334 (0CE01), the upper 8 bits of PQW carry the active D/A code. The lower 8 bits are ignored. This is exactly the left-justification principle that allows FC106 to remain unchanged.

10. Linear Custom Scaling Alternative

For projects that want to bypass FC106 entirely — for example, to avoid the Standard Library dependency — a generic scaling FC can be written with the following interface and body.

FUNCTION FC 200 : VOID
VAR_INPUT
  IN        : REAL;   // raw input
  IN_MIN    : REAL;   // 0.0
  IN_MAX    : REAL;   // engineering max, e.g. 100.0
  OUT_MIN   : REAL;   // 0.0
  OUT_MAX   : REAL;   // 255.0 for 8-bit, 4095.0 for 12-bit
END_VAR
VAR_OUTPUT
  OUT       : INT;    // scaled output
  ERR       : BOOL;   // overflow flag
END_VAR
BEGIN
  IF IN_MAX <= IN_MIN OR OUT_MAX <= OUT_MIN THEN
    OUT := 0;
    ERR := TRUE;
    RETURN;
  END_IF;
  OUT := REAL_TO_INT( (IN - IN_MIN) * (OUT_MAX - OUT_MIN)
                      / (IN_MAX - IN_MIN) + OUT_MIN );
  IF INT_TO_REAL(OUT) < OUT_MIN OR INT_TO_REAL(OUT) > OUT_MAX THEN
    ERR := TRUE;
  ELSE
    ERR := FALSE;
  END_IF;
END_FUNCTION

This block accepts the physical code range directly (0…255, 0…4095, 0…27648) as OUT_MAX, eliminating the headroom math described in Section 5. Use it when the FC106 library is unavailable or when the engineering range is small and the 27648 multiplier loses useful resolution.

11. Comparison: FC106 vs Custom Scaling on Sub-16-bit Modules

Criterion	FC106 (UNSCALE)	Custom FC200 (Section 10)
Library dependency	STEP 7 Standard Library	None
Output range	Fixed 0…27648 (or -27648…+27648)	Configurable (0…255, 0…4095, etc.)
Resolution usage on 8-bit	~93.75% of 27648 range (top 8 bits only)	100% of available codes
Bipolar support	Built-in via BIPOLAR	Manual via IN_MIN negative
Overflow detection	RET_VAL W#16#0008 / 0100	ERR BOOL
CPU load	~120 µs typical (CPU 315-2 PN/DP)	~45 µs typical
Migrating module resolution	No code change required	Code change required

12. Related Siemens Standard Functions

• FC105 (SCALE) — converts 0…27648 integer to REAL engineering range. The forward direction of FC106.
• FB41 (CONT_C) — continuous PID controller, expects the I/O at 0…27648 and 0…100% setpoint.
• FB100 to FB113 — curve linearization, integration, derivative blocks used for nonlinear scaling on temperature and other sensors.
• FC201 to FC206 (TIA Portal PID Compact) — successor to FB41 in TIA Portal V13 SP1 and later, retains the 0…27648 convention.

All of the above are documented in the Siemens Scaling and Unscaling Analog Values application note.