S7-300 OB35 Cyclic Interrupt: Setting Scan Time for Analog Reads

Overview: Cyclic Interrupt Organization Blocks in SIMATIC S7-300

Organization blocks (OBs) form the interface between the SIMATIC S7-300 operating system and the user program. They are called by the operating system and control how and when user code executes. Siemens documentation describes OBs as the structural elements that determine the response to specific events such as startup, errors, hardware interrupts, and—most relevant here—cyclic interrupts.

A cyclic interrupt OB (OB30 through OB38 on most S7-300 CPUs) is one of the event-driven OBs in the S7-300 family. The CPU interrupts the main scan (OB1) at a fixed, configurable interval, executes the cyclic OB, returns to OB1, and resumes the previous RLO (result of logic operation) state. This makes cyclic OBs ideal for deterministic periodic sampling, supervisory watchdog logic, and any function that must run at a fixed rate independent of OB1 scan jitter.

The user requirement described in the source case is simple: read and scale an analog input every 30 seconds (or 60 seconds) using FC105. Because the analog front end takes ~22 ms per channel on a SM 331-7KF02 and ~176 ms for the full module, the natural question becomes whether the cyclic OB period must exceed the conversion time. The short answer is no, but the design discipline behind the answer matters and is detailed in the sections that follow.

Prerequisites

• STEP 7 V5.5 (or compatible) with HW Config installed. STEP 7 V5.6 is the final classical version before TIA Portal migration.
• SIMATIC S7-300 CPU 312C (6ES7312-5BE03-0AB0 or comparable compact CPU with integrated I/O and analog capabilities), or any CPU 31x that supports OB3x. CPUs without OB3x support (e.g., CPU 312, CPU 314 if older) require the IEC timer fallback described later.
• SM 331 analog input module (in the source case, 6ES7331-7KF02-0AB0) configured for the desired measurement range and integration time.
• FC105 (SCALE) library block from the STEP 7 Standard Library → "TI-S7 Converting Blocks" → FC105, or the equivalent "SCALE" function.
• Programming device with MPI or PROFIBUS connection to the CPU.

Organization Block Catalog for the S7-300

The S7-300 supports nine classes of organization block. Understanding which class an OB belongs to is critical: a cyclic interrupt OB cannot be created or downloaded if the CPU firmware does not support that specific OB number.

OB30 through OB38 are cyclic; OB40 is a hardware interrupt; OB10 is a time-of-day interrupt. Newcomers frequently confuse them. The source question uses the phrase "OB30 means the program will read from sensors every 5 seconds." That interpretation is partly correct and partly wrong: OB30 is a cyclic interrupt, but its default period is not 5 s and OB30 is not necessarily available on the CPU 312C.

CPU 312C OB Support Matrix and Why OB30 May Not Exist

CPU class and firmware determine which cyclic OBs can be loaded. The CPU 312C compact (6ES7312-5BE03-0AB0) exposes only OB35 as a cyclic interrupt, and only at a default period of 100 ms. It does not accept OB30, OB31, OB32, OB33, OB34, OB36, OB37, or OB38. If the project contains an OB30 source file and you try to download it, STEP 7 reports error 0x8001 / SF: OB not supported by CPU.

The CPU 315-2 DP, 317, and 319 do support OB30. On those CPUs, OB30 carries a default period of 5 000 ms. The phrasing "OB30 means read every 5 seconds" in the source is therefore correct for a 315-2 DP, but on a 312C the answer is simply: OB30 is not a usable block on that CPU—use OB35 and change its period.

Configuring OB35 Period in HW Config (Step-by-Step)

The 30-second and 60-second periods requested in the source question are well within the 1 ms – 60 000 ms range available on every supported CPU. The period is changed in HW Config, not inside the OB itself.

1. Open SIMATIC Manager → your S7 project → the S7-300 Station object.
2. Double-click Hardware to launch HW Config.
3. In the station window, click the CPU icon (rail position 2 or 3 depending on the configured rack). The CPU properties dialog opens on the right.
4. Select the Cyclic Interrupts tab. You will see one row for OB35 with two editable columns: Execution (enable/disable) and Period (ms).
5. Tick the Execution checkbox for OB35. If the box is not ticked, OB35 is not started by the operating system even if the block exists in the program.
6. Set Period (ms) to 30 000 for a 30-second sample rate, or 60 000 for a 1-minute sample rate. The field accepts integer milliseconds; do not enter units.
7. Click OK, then Station → Save and Compile (Ctrl+S). This generates the system data blocks (SDB) that the CPU uses to configure its interrupt sources.
8. Download the hardware configuration to the CPU (PLC → Download to Target → CPU). A prompt warns that the CPU will stop; acknowledge and let it run back up.
9. Create or open OB35 in your program. Place the call to FC105 inside OB35. Make sure FC105 is unconditional inside the OB—OB35 already runs at the desired rate, so a gate inside the OB is redundant.
10. Download the program blocks (OB35, FC105, the FC105 instance DB if used, and any background DB) to the CPU.

Verification with STEP 7 Online Diagnostics

After download, confirm the new period is in effect using PLC → Module Information → Cyclic Interrupts. The dialog reports each OB3x number, the configured period, and the measured time between last two calls. If the reported period does not match the value entered, the CPU has not yet picked up the new SDB—power-cycle the CPU or run PLC → Clear/Reset → Cold Restart to force a re-read of the system data.

Inside OB35: Calling FC105 (SCALE) Correctly

FC105 (also exported in TIA Portal as the SCALE function block) converts a raw integer from the analog input (PIW address) into an engineering-unit real (output in MD / DBx.DBD). The call inside OB35 looks like the following STL snippet (or its LAD/FBD equivalent):

// OB35 – Cyclic interrupt, e.g. period 30000 ms
// Input:  PIW 288  (channel 0 of slot 4 SM 331-7KF02)
// Outputs: scaled engineering value in MD100 (REAL)
// Bipolar: FALSE  (e.g. 0–10 V sensor)
// LO_LIM  :  0.0
// HI_LIM  : 100.0

CALL  FC105
      IN  := PIW288
      HI_LIM := 1.000000e+002
      LO_LIM := 0.000000e+000
      BIPOLAR := FALSE
      RET_VAL := MW110
      OUT := MD100

Parameters to verify before commissioning:

• IN: PIW address of the channel being read. The address depends on slot and channel; for slot 4 / channel 0 of an S7-300 it is typically PIW 288 (byte 36) – PIW 302 (byte 38). Check with HW Config → SM 331 → Addresses.
• BIPOLAR: FALSE for unipolar inputs (0–10 V, 0/4–20 mA), TRUE for bipolar inputs (±10 V, ±20 mA).
• LO_LIM / HI_LIM: engineering unit range. Do not confuse this with the raw count range (0–27648 for unipolar, –27648…+27648 for bipolar on a 12/13/14-bit SM 331).
• RET_VAL: word for FC105 return value. 0 = OK; non-zero = error (see STEP 7 help).
• OUT: REAL destination (MD, DBD, or symbolic tag). FC105 does NOT retain the value; you must move it to a DB yourself if you want history.

Alternative: IEC Timer in OB1 (No OB3x Required)

If the target CPU does not support any OB3x (for example, the older CPU 312 without "C" suffix), the standard solution is to use a self-resetting pulse timer inside OB1 to gate the FC105 call. This is functionally equivalent to a 30-second cyclic interrupt for a 30-second sampling rate, with one important difference: the timing now depends on OB1 scan time, so if OB1 ever exceeds 30 s the period slips. With FC105 and a healthy program that is never an issue, but document the assumption.

// OB1 – Main scan, calls FC105 once every 30 s
// SFB4 / SFB5 are IEC 61131-3 timers in the STEP 7 Standard Library
// Alternative: use FB / SFB3 (TP), SFB4 (TON), SFB5 (TOF)
// Here we use a 30 000 ms pulse generated by TOF self-reset:

      U     M     30.0          // "SampleTick" latching bit
      UN    M     30.1          // "SamplePulse" 1-scan enable
      S     M     30.1
      U     M     30.1
      L     S5T#30S             // 30-second period
      SD    T     30            // pulse timer
      U     T     30
      =     M     30.0          // re-trigger on timer expiry
      NOP   0
      U     T     30
      SPBNB _001
      CALL  FC105
            IN  := PIW288
            HI_LIM := 1.000000e+002
            LO_LIM := 0.000000e+000
            BIPOLAR := FALSE
            RET_VAL := MW110
            OUT := MD100
_001: NOP   0

For TIA Portal, the equivalent uses an IEC_TIMER_0_1 instance (TP / TON / TOF) inside an FB that is called from OB1. The principle is the same: a pulse of width ≥ 1 OB1 scan every N seconds, and the FC call gated on the pulse edge.

The timer-based approach is generally preferred for slow sampling (1 minute, 5 minutes) because:

• It does not consume one of the CPU's scarce OB3x resources.
• It is portable to smaller CPUs that lack OB3x support.
• The 1-minute rate is so slow that the OB1 vs OB3x latency distinction is academic for an analog input application.

Analog Module Conversion Time: SM 331-7KF02 Reference

The original question raises an important design concern: the analog-to-digital conversion time. On the SM 331-7KF02 (6ES7331-7KF02-0AB0), the conversion time depends on the integration-time/frequency-rejection selector and the resolution of the active channels.

For the 30-second application described in the source, conversion time is irrelevant. The SM 331 returns the converted value to the PIW input image almost immediately after the conversion cycle completes; the value is held in the input image until the next PIW read or the next conversion cycle. There is no need to set the cyclic interrupt period longer than 176 ms. The only time the OB3x period must exceed the conversion time is when you are explicitly synchronizing logic to a single conversion edge—in which case you would normally trigger from the SM 331's hardware interrupt (OB40) wired to "conversion complete," not from a software timer.

OB Priority and Watchdog Interaction

OB3x priorities are set in HW Config → CPU properties → "Cyclic Interrupts" tab → "Priority" column. Default priorities:

Because OB3x priorities are higher than OB1, a long-running OB3x can starve OB1, and a runaway OB3x will be detected by the CPU's scan-time watchdog. Default watchdog time is 150 ms for OB1; OB3x each have their own (default 100 ms, configurable up to 60 000 ms in some CPUs). If you set OB35 to 30 000 ms and your FC105 call takes 5 ms, you are well within the watchdog budget. If you mistakenly configure OB35 priority above OB40 and both fire simultaneously, the second one will queue, then time out and trigger OB80 (time fault).

Step Sequence Timing Diagram

The following inline SVG illustrates the OB1 / OB35 interleaving for a 30-second OB35 period. OB1 is interrupted at the configured phase offset and resumes seamlessly afterwards.

Verification Procedure

1. Open VAT (Variable Table) and monitor MD100 (the FC105 output) and MW110 (FC105 RET_VAL).
2. Set a force or input a known voltage on the SM 331 channel. The scaled value should change only on every 30-second OB35 fire, not on every OB1 pass.
3. Confirm with PLC → Module Information → Statistics that OB35 entry count increments by 1 every 30 s.
4. Check Diagnostic Buffer for OB85 entries (OB3x called and not loaded—indicates a missing OB), or OB80 entries (OB3x time fault—indicates the period is shorter than the execution time).
5. Cross-check the diagnostic event "Cyclic interrupt OB35 time error" and verify that your configured period (30 000 ms or 60 000 ms) matches the value in HW Config.

Troubleshooting Matrix

Common Mistakes and Field-Proven Caveats

• Editing the OB number: You cannot "promote" OB35 to OB30 by renaming the block. The OB number is part of the OB's system-level identity (its priority and call source) and must match the CPU firmware. Renaming an FB to OB30 will fail the download.
• Forgetting the hardware download: A common student mistake is to write FC105 in OB35 inside LAD/STL/FBD, change the period text in the OB header comment, and download only the blocks. The period in the comment is decorative; only the SDB period value is real.
• Confusing OB35 with OB40: OB35 is cyclic (time-driven), OB40 is hardware-interrupt (event-driven). Use OB40 if you need to react the instant the SM 331 finishes a conversion.
• Confusing OB3x priority with the OB1 priority: OB3x priorities are higher than OB1. If two OB3x fire in the same millisecond, the second one waits, and may time out if its watchdog is short.
• Forgetting that the input image is updated only at OB1 start (and at OB40 for hardware-interrupt modules): If OB35 reads PIW288 outside the input-image refresh, it still gets the most recent value because the SM 331 back-fills the PIW at the end of its own conversion cycle, but on some older modules the PIW can briefly hold a stale value. Always allow at least one full conversion cycle between power-on and the first valid read.
• Not handling FC105's output during warm restart: After a warm restart, FC105's OUT may retain its last value (or be 0, depending on the OB's instance-data reset behavior). For safety-critical loops, explicitly initialize MD100 to 0 at startup (e.g., in OB100).

OB and Block Type Summary (for STEP 7 Help Lookup)

Frequently Asked Questions