S7-300 PID Voltage Control with Digital Potentiometer Actuator

System Overview

This reference covers a closed-loop voltage regulation retrofit for an existing multi-transformer DC bus originally trimmed by an operator turning a panel potentiometer. The objective is to keep the bus voltage inside a defined band (35-41 V DC in the source application) by replacing the manual pot with a current- or voltage-controlled digital potentiometer driven from a Siemens SIMATIC S7-300 CPU 315-2 DP PID loop. The same architecture applies to any slow electrical process: DC link voltage, generator field voltage, electrolyzer voltage, or static exciter field.

The control loop has three sections:

• Process measurement: A DC voltage transducer (for example 0-50 V input, 4-20 mA output) drops the bus voltage into a range accepted by an S7-300 SM331 analog input module.
• Controller: The S7-300 CPU executes the standard continuous PID block (FB41 CONT_C from the STEP 7 Standard Library) with the measured value as PV and an operator-entered or recipe-driven value as SP.
• Final element: An analog output module (SM332) drives a 4-20 mA-to-resistance converter (digital potentiometer) that replaces the operator's hand pot. The wiper of the digital pot is wired into the existing control circuit (saturable reactor, motorised variac, or static exciter) so the PID output controls the same point the operator used to.

Hardware Selection

CPU and rack

The CPU 315-2 DP referenced in the source is a classic S7-300 processor. Common catalog variants include the 6ES7315-2AF03-0AB0 or later 6ES7315-2AH14-0AB0, each delivering 128 KB / 256 KB of work memory, a PROFIBUS DP master/slave interface, and 24 V DC power. The DP suffix is irrelevant to the PID function but is useful if the cell is integrated into a larger PROFIBUS or PROFINET line. For more details, refer to the S7-300 product page on the Siemens S7-300 product page and the documentation index on the Siemens Industry Online Support portal.

Analog input module

For a single voltage loop, an 8-channel SM331 is the typical choice. Use a 4-wire current input channel configured for 4..20 mA in HW Config. Two common part numbers:

The 16-bit module reduces the LSB to roughly 0.76 mV on a +/-10 V range, which is finer than the 13-bit alternative and reduces quantization-induced jitter that would otherwise force a wider dead-band.

Analog output module

The SM332 family supplies the 4-20 mA drive to the digital potentiometer. Use a 4-20 mA current output (not voltage) when the digital potentiometer is loop-powered:

With a 4-20 mA output the 16-bit module resolves to roughly 0.244 uA per LSB, which is well below any noise floor the actuator will see.

Digital-to-potentiometer converter

Two commercial units are typically used in this kind of retrofit:

1. Edisa DGP00 - 4-20 mA input, 100 ohm / 1 kohm / 10 kohm wiper output. The Edisa DGP00 product page lists it as a DIN-rail mounted, loop-powered solid-state substitute for a manual pot.
2. APCs ATP168 Analog-to-Potentiometer - documented in the APCs ATP168 reference design as a voltage- or current-driven resistance output.

When sizing, three parameters must be matched:

• Input signal range (4-20 mA vs 0-10 V) must match the SM332 output configuration.
• Wiper resistance range must match the existing manual pot (typically 1 kohm, 5 kohm, or 10 kohm linear).
• End-to-end resistance must be at least an order of magnitude higher than the load it controls, so the converter does not have to dissipate significant power.

Power supply

A 6ES7307-1EA01-0AA0 (PS 307, 5 A) covers the CPU and a single AI/AO pair. If the digital potentiometer is loop-powered from the 4-20 mA output, no separate supply is required for the actuator.

Signal Conditioning for the 32-41 V Bus

If a 4-20 mA transducer is not already installed on the DC bus, the input can be derived from a passive resistor divider. Given a 0-50 V bus, a 4:1 divider (for example three 100 kohm in series with a 33 kohm to ground) presents 10 V at the top of the divider when the bus is at 50 V and 8.2 V at 41 V. The scaling line is then:

• 0 V bus = 0 V divider = 0 mA (4 mA offset if 4-20 mA transducer is used)
• 35 V bus = 7.0 V divider
• 41 V bus = 8.2 V divider
• 50 V bus = 10 V divider

A 1 Mohm total divider draws 50 uA at 50 V, which is negligible compared to the bus capacity, but the divider must be referenced to a clean analog ground at the SM331. Use 0.1 percent or better metal-film resistors if you intend to derive the engineering range from the divider alone; a typical 1 percent divider will introduce 0.25 V of error at the 41 V setpoint.

For a 4-20 mA transducer the engineering scale is:

where AI_raw is the value returned by the S7-300 analog input driver (0-27648 integer, signed 16-bit word), and V_min / V_max are the engineering zero and full scale of the transducer. For a 0-50 V transducer the formula simplifies to:

For a 0-10 V analog output, the manipulated value scaling to PQW is:

Analog I/O Wiring

For 4-wire current input on SM331:

Transducer (+) --- Channel n+ (Pin 2 of the AI front connector)
Transducer (-) --- Channel n- (Pin 3)
Transducer V+ --- 24 V DC (separate supply)
Transducer V- --- 24 V return

For 4-20 mA current output on SM332 to a loop-powered DGP00:

SM332 AQ0+ --- DGP00 IN+
DGP00 IN- --- SM332 AQ0-
(Loop is completed through the converter internal shunt)

PID Implementation with FB41 CONT_C

The S7-300/400 firmware library (STEP 7 V5.x) provides the FB41 "CONT_C" continuous PID controller. It is the standard block for slow electrical control and is referenced in the Siemens Industry Online Support documentation library. For a general overview of PID theory and architecture, see the National Instruments PID theory primer, the Wikipedia PID controller entry, and the DigiKey "How to Control Output Voltage using a PID" tutorial. A TIA Portal target can use the equivalent PID_Compact block in the PID_Compact library.

FB41 inputs and outputs

For voltage control of a slow thermal/electrical process, a 100-250 ms scan is appropriate. Faster than 50 ms is rarely useful because the field response is dominated by L/R time constants on the order of hundreds of milliseconds.

Sample ST code for FB41 instance

// Voltage PID - FB41 instance
DATA_BLOCK "DB_VoltPID"
    "CONT_C"    // FB41 instance body
BEGIN
    SP_INT   := 38.0;          // Setpoint 38 V
    PV_IN    := "DI_Voltage".EngVal;
    PV_PER   := 0;
    MAN      := 0.0;
    MAN_ON   := FALSE;
    GAIN     := 0.8;
    TI       := 20.0;
    TD       := 0.0;
    TM_LAG   := 0.0;
    DEADB_W  := 0.1;
    LMN_LLM  := 0.0;
    LMN_HLM  := 100.0;
    PV_FAC   := 1.0;
    PV_OFF   := 0.0;
END_DATA_BLOCK

// In OB35 (cyclic interrupt 100 ms)
CALL "CONT_C", "DB_VoltPID"
    SP_INT   := "DB_VoltPID".SP_INT
    PV_IN    := "DI_Voltage".EngVal
    MAN      := 0.0
    MAN_ON   := FALSE
    GAIN     := "DB_VoltPID".GAIN
    TI       := "DB_VoltPID".TI
    TD       := "DB_VoltPID".TD
    LMN_PER  := "PQW_VoltageOut";

LMN_PER is preferred for the SM332 because the controller writes the manipulated value directly to the analog output peripheral (0-27648) and avoids a second engineering-to-raw conversion.

Dead-band and limits

For a 35-41 V control band the engineering span is 6 V. The dead-band should be set to 0.05-0.1 V (1-2 percent of span) to suppress noise-driven cycling when the bus is steady. Manipulated value limits clamp the output to the physical range of the digital potentiometer; for a 4-20 mA actuator, LMN_LLM = 0 percent and LMN_HLM = 100 percent ensure the loop never commands outside the converter's input range.

PID Tuning

Use this three-step procedure for the FB41 voltage loop:

1. Manual step test. Set MAN_ON = TRUE and drive MAN from 0 percent to 100 percent in 5 percent steps. Log PV. The process curve identifies the process gain Kp_process (engineering units per percent LMN) and the dominant lag tau_p.
2. P-only critical gain. Switch to automatic with TI = very large, TD = 0. Increase GAIN until the loop oscillates continuously. Critical gain Kc and period Pc give Ziegler-Nichols starting values: GAIN_start = 0.5 * Kc TI_start = 0.8 * Pc TD_start = 0
3. Fine tune. Step the setpoint 1 V up and 1 V down. Adjust GAIN for fast rise without overshoot greater than 5 percent, then reduce TI by 20 percent at a time until the loop returns to setpoint in 2-3 cycles with no oscillation. Add a small TD only if the saturable reactor shows mechanical/electrical lag.

For voltage control, the system is normally overdamped by the L/R time constant of the field winding, so P-only is often sufficient and the integral term handles offset. If a saturable reactor is in the loop, the magnetising curve introduces nonlinearity; a derivative term on PV helps anticipate the field response. Tuning-time formulas useful in this step are:

where zeta is the damping ratio you read off the step response. Targets for a 6 V span are zeta between 0.7 and 1.0, overshoot between 2 percent and 6 percent, and settling time under 3 s for a 1 V setpoint step.

Anti-Windup and Bumpless Transfer

FB41 integrates an internal anti-windup that holds the integrator when LMN is at LMN_LLM or LMN_HLM. To preserve anti-windup, do not clamp LMN downstream of the block; instead, set LMN_LLM and LMN_HLM to the physical range of the actuator (for example 0 percent and 100 percent).

Bumpless transfer from manual to automatic is critical when the operator is still commissioning. The integrator must be pre-loaded so LMN at the moment of switching equals the manual MAN value. With FB41 the procedure is:

1. Run the block in manual mode for at least 5 cycles so I_ITVAL settles to MAN.
2. Click "Update" in the PID control panel (or write 1 to the COM_RST input) so the integrator takes the MAN value as its initial state.
3. Switch MAN_ON from TRUE to FALSE. The transition is bumpless only if SP_INT and MAN are within 50 percent of each other; outside that range the block ramps the output smoothly.

Safety Considerations

• The DC bus is at 32-41 V, which is below the 50 V SELV threshold but can deliver hundreds of amps through 4 parallel Lincoln transformers. The current loop is a burn and arc-flash hazard; the control wiring must be physically segregated from the power cabling.
• Wire the digital potentiometer in parallel with the existing manual pot, with a manual/auto selector switch. This allows the operator to override the PID in case of a sensor failure or PID instability.
• Add a hardwired interlock that opens the field contactor if the measured bus voltage exceeds 43 V (1 V above the operator's manual limit) for more than 5 s. This backstop runs in the PLC's discrete I/O and does not depend on the PID path.
• Configure a watchdog on the analog output: if FB41 is no longer called in OB35 for more than 1 s, force the SM332 to 0 percent (4 mA) using the analog output default. The digital potentiometer should be configured to "fail to mid-scale" or "fail to 0 percent" based on the actuator's safe state.
• Fuse the 4-20 mA loop and the transducer supply independently of the PLC supply so that a short on the field side does not crash the SIMATIC rack.
• Enable SM331 diagnostic interrupts in HW Config. A wire break on the AI raises a diagnostic OB (OB82) which can drop LMN_PER to 0 percent and trip the interlock within one scan.

HMI Integration

Display on the HMI (WinCC flexible or TIA Portal Panel) the following fields:

• Setpoint (operator entry, 30-43 V, clamped in HMI).
• Process value (live, decimal).
• Manipulated value (0-100 percent).
• Loop mode (AUTO / MANUAL).
• Controller deviation (SP - PV).
• I_ITVAL and PV_FAC for diagnostics.
• Alarm history for PV_HI, PV_LO, AI break, watchdog timeout.

Allow the operator to switch to MANUAL and drive LMN from a slider; this is the primary commissioning tool and the primary fallback when the bus is unstable. Display the GAIN, TI, and TD as live fields and write them back to the instance DB so that tuning changes do not require an online download.

Commissioning Checklist

1. Verify the polarity and scaling of the voltage transducer on the bench with a calibrated source.
2. With the field contactor OPEN, force the SM332 to 0 percent, 50 percent, and 100 percent and confirm the digital potentiometer wiper moves to the expected resistance. For a 1 kohm pot, 0 percent should read near 0 ohm wiper-to-end, 50 percent near 500 ohm, 100 percent near 1 kohm.
3. Engage the field with a 5 percent LMN step and observe PV; confirm the polarity (raising LMN should raise PV, otherwise swap the wiring at the digital pot or invert GAIN).
4. Run the P-only step test, record Kc, and compute initial GAIN/TI.
5. Switch to AUTO and walk the setpoint through 35 V, 38 V, 41 V; observe the response. Acceptable overshoot is 1-2 percent on a 6 V span.
6. Force a perturbation: bump the load current or step a parallel transformer on/offline. The loop should recover in 2-4 cycles without ringing.
7. Trip the watchdog: pull the analog input transducer. The PLC should drop LMN to 0 percent (4 mA) within the watchdog time and the interlock should open the field contactor.
8. Hand back to OPERATOR AUTO with a written record of the final GAIN, TI, TD, and dead-band values.

Troubleshooting Matrix

Frequently Asked Questions