S7-300 Pulse Generation for Motion Sync: FM 352-5 Module Guide

Overview: Pulse Generation as a Master Clock Source

Driving a bank of servo inverters or variable frequency drives (VFDs) from a single master clock generated by an S7-300 CPU 315F-2 DP is a recurring requirement in converting lines, packaging machinery, and web-handling applications. The specification in the source brief calls for a clock signal that is fed into a downstream controller (often a SIMOTION, SINAMICS, or third-party motion controller) so that all axes can be tied to a common reference. The fundamental engineering question is not whether the PLC can toggle a digital output, but whether the resulting signal has the deterministic edge-to-edge timing required to keep a moving web or chain in registration.

Before selecting any module, calculate the required pulse rate. The two operating modes in the brief translate as follows:

Use the general form f_pulse (Hz) = resolution (pulses/mm) × linear_speed (mm/s). For any axis synchronisation problem the same formula applies with the encoder-pitch substituted for the linear travel.

Why Standard Digital Output Modules Cannot Hold the Rate

When a standard SM 322 DO module is commanded from OB1, the latency stack between the CPU's logical decision to set the bit and the physical transition of the field terminal includes:

1. OB1 scan completion and PIQ transfer time
2. Backplane bus update on the ET200S station (IM 151-1 HIGH FEATURE 6ES7151-1BA02-0AB0)
3. PROFIBUS DP cycle time if the ET200S is on DP
4. Module-internal output-driver propagation delay (typ. 50–100 µs for SM 322)
5. Optocoupler and output-stage rise/fall time

The dominant contribution is the application scan. A typical CPU 315F-2 DP with mixed bit/word logic and a few FB calls runs OB1 in 8–15 ms. To generate a 400 Hz square wave from a single bit toggled each cycle, the scan must be at most 1.25 ms. To generate 4,000 Hz the scan must be ≤ 125 µs. Neither value is achievable in OB1 on a 315F-2 DP for any real production program.

Even if the scan were fast enough, jitter is the deal-breaker. Field experience has shown that a routine clock generated in OB1 with the cycle held at ~10 ms can stretch to 65 ms when communications overhead, alarm tasks, or math blocks temporarily extend the cycle. A 65 ms low period followed by a 10 ms high period produces a frequency that swings from 13 Hz to 50 Hz, and worse, the edge-to-edge distance at 400 mm/s drifts between 5.2 mm and 26 mm. That is exactly the failure mode that has been documented in the field: mis-synchronised axes, web stretch, and mechanical damage in the worst case.

Frequency Budget by Hardware Class

For the 100–400 Hz requirement (1 pulse/mm mode) the FM 350-1, the FM 352-5, and the ET200S 1Count 24V all have more than 10× margin. For the 4,000 Hz requirement (1 pulse/0.1 mm) all three still hold, but the standard-DO and OB35 solutions are excluded.

FM 352-5 High-Speed Boolean Processor

The recommendation in the engineering community for high-speed pulse generation on S7-300 is the FM 352-5. The device is a self-contained, electrically isolated 12-output high-speed logic module that runs independently of the OB1 cycle. The CPU downloads a configuration (a chain of AND/OR/TIMER/COUNTER/OUTPUT operations, plus cam-style switching) and the FM executes it on its own internal scan, typically 1 µs per instruction.

The FM 352-5 fits a standard S7-300 rail slot and is configured as a single analog or function module slot in HW Config. The user programs a sequence of boolean operations that toggle the output on a time or count basis; the CPU only writes a frequency setpoint and reads a status word. Because the FM keeps toggling the output on its own, the result is unaffected by OB1 jitter.

Configuration in HW Config (Step 7 V5.5 / TIA Portal V16+)

1. Insert the FM 352-5 into the S7-300 station. Allocate a free slot; the FM cannot share a slot group with SM modules.
2. Open the module properties and assign inputs DI0–DI7 to the events you want to act on (for a simple clock, none — use the on-board counter).
3. Open the FM 352-5 configuration editor and place an OUTPUT element on the ladder rung. Wire a TIMER (set to 0.5 / f_desired) to the output.
4. For dynamic speed changes, expose the timer preset as a DBW interface. The CPU writes the new value (in µs) on each ramp step, the FM updates on the next internal cycle.
5. Download the HW Config and the FM configuration to the CPU. The FM self-initialises on CPU restart.

ET200S Counter Module Approach

For installations where the CPU 315F-2 DP drives an ET200S station with IM 151-1 HIGH FEATURE, the 1Count 24V (6ES7138-4DA04-0AB0) is a more compact solution. The 1Count module can be configured as a pulse generator with a frequency range of 0.1 Hz to 10 kHz, and it can be gated and re-parameterised on the fly through process data.

Setpoint write in S7 is a simple PQW transfer:

// Frequency setpoint in 0.1 Hz LSB. 4000 Hz = 40000 dec.
L 40000
T PQW 304    // slot 4 base address; adjust to ET200S slot 1

For a smooth 100 → 300 Hz ramp, drive the PQW from an OB35 block (e.g. 100 ms) that adds a fixed increment per call. The module will accept each new setpoint at the next internal update without dropping a pulse.

FM 350-1 Counter Module (High-End)

For installations that exceed 10 kHz or that need quadrature simulation, the FM 350-1 counter (6ES7350-1AH03-0AE0) is the next step. It is a single-channel counter with an internal DSP for fast comparison and pulse-train generation.

Use the FM 350-1 when a system later requires encoder simulation or when the master clock has to be derived from a closed-loop ratio against a process variable (e.g. dancer position, line speed feedback).

OB35 Cyclic Interrupt — Limited Use

OB35 is a time-of-day interrupt that runs at a fixed interval set in HW Config (1 ms to 60,000 ms). It is deterministic relative to itself but not to the I/O update, because OB35 simply pre-empts OB1 at its scheduled time. For a clock generator, OB35 can be used as a high-level timer: the OB increments a counter, the program toggles a bit when the counter equals the half-period, and a SM 322 DO echoes the bit. With OB35 at 2 ms, the maximum square-wave frequency is 250 Hz with 2 ms jitter — and the jitter is exactly the OB period, which is unacceptable for axis sync above ~10 Hz.

Therefore OB35 is not a valid clock source. It is suitable for re-parameterising the FM 352-5 or 1Count module at a smooth rate, e.g. to ramp from 100 Hz to 300 Hz over 5 seconds (500 increments at 10 ms).

// OB35 — 10 ms cycle, ramp 100 Hz to 300 Hz over 5 s
// Setpoint written to 1Count at PQW 304 (0.1 Hz units)
      L     DB10.DBW 0       // current setpoint (0.1 Hz)
      L     2                // step = 0.2 Hz / 10 ms = 20 Hz/s
      +I
      T     DB10.DBW 0
      L     3000             // limit 300.0 Hz = 3000 dec
      <I
      JC    RAMP
      L     3000
      T     DB10.DBW 0
RAMP: L     DB10.DBW 0
      T     PQW 304

PROFINET IRT and Isochrone Mode

The most modern and deterministic approach on a SIMATIC system is PROFINET IRT (Isochronous Real-Time). With an isochrone-capable IM (e.g. IM 151-3 PN on ET200S) and an isochrone counter module, the entire path from the CPU's clock to the output terminal is synchronised to a fixed network cycle. Edge jitter drops to sub-microsecond.

To enable isochrone mode, set "Constant bus cycle time" in HW Config under the DP master system properties and tick "Isochrone mode" on the slot that holds the counter module. The Ti and To times must be entered; typical values for the 1Count 24V are Ti = 250 µs, To = 100 µs.

Drive-to-Drive Synchronisation — The Architecturally Cleaner Choice

Generating a clock from any PLC and then shipping it down a wire to a separate motion controller introduces two new failure modes: cable break, and ground-loop noise on the clock edge. For new designs, evaluate the drive-native alternatives first.

• SINAMICS S120 with CU320-2: SIMOLINK fibre-optic ring for deterministic, cycle-tied distribution of setpoints between drives. Up to 200 nodes, sub-microsecond synchronisation.
• SINAMICS S120 with CU310-2: Master/slave position control over PROFIdrive telegram 110 — drive to drive, no PLC in the loop.
• Allen-Bradley Kinetix 6500: CIP Motion on EtherNet/IP with Time Sync (IEEE 1588) — drive-to-drive only, PLC acts as configurator.
• Yaskawa Sigma-7 / MP3300iec: MECHATROLINK-III motion bus.

For the application described, the SIMOLINK ring between SINAMICS S120 drives is often the most robust solution, because the master clock is generated by the first drive's encoder, not by the PLC. The PLC only needs to command the desired ratio through PROFIdrive.

Wiring and EMC Considerations

1. Run the clock pair (24 V output and 0 V return) in a shielded twisted pair. Ground the shield at the source end only.
2. Keep the clock cable in its own tray, at least 200 mm from VFD power cables. Cross at 90° if a crossing is unavoidable.
3. Provide a 24 V DC suppressor (1N4007 reverse-biased, or a TVS) at the receiving controller's terminal block, especially when the cable run exceeds 10 m.
4. Set the receiver's input filter to the minimum value that rejects the expected noise. A 0.5 ms input filter cuts the noise band but does not affect a 100 Hz to 4 kHz clock.
5. Use a pull-up resistor on the receiver side (typically 2.2 kΩ to 24 V) only if the receiver is a sinking input; sourcing outputs of the SM/FM do not need it.

Verification and Commissioning Checks

Troubleshooting Matrix

Recommended Configuration Summary

References to Official Documentation

• Pulse generator (S7-300, S7-400) — PID control, TIA Portal documentation
• Siemens Industry Online Support — product manuals and FAQs

Frequently Asked Questions