S7-300 STL RLO Behavior: A and JC Jump Instruction Trace

Overview

When an S7-300 CPU executes a Statement List (STL) program, every bit-logic instruction (A, AN, O, ON, X, XN, etc.) and every assignment or jump depends on a single internal bit called the Result of Logic Operation (RLO). A frequent source of confusion for engineers new to S7-300 STL is the value of the RLO at the start of a network, the way the RLO is updated by an A instruction, and the way the conditional jump JC rewrites the RLO when the jump is not taken. This reference walks through those mechanics in detail using the canonical four-statement network shown below and resolves the underlying questions about the RLO before, during, and after each step.

| Network 1
1:  A   M 0.0
2:  JC  L1
3:  A   M 0.1
4:  JC  L2

The RLO behavior described in this article applies to all S7-300 CPUs (CPU 31x series, for example CPU 315-2 PN/DP), to S7-400 CPUs, and to the ET 200S/IM 151 CPUs that share the same STL instruction set. The semantics are documented in the Siemens "Programming and Operating Manual - Statement List for S7-300/400" and are invariant across STEP 7 V5.5, V5.6, and the S7-300 compatibility mode of TIA Portal.

RLO and Status Word Architecture

The S7-300 CPU maintains a 16-bit internal register called the Status Word (STW). Bits 0 through 8 of the STW are updated implicitly by nearly every bit-logic, comparison, and arithmetic instruction. STL programmers interact with the STW most often through the RLO, but several other bits are equally important when reasoning about jumps and first-check behavior.

The RLO is bit 1 of the status word. It is the only bit that drives JC in the network above. The state of the RLO can be inspected at runtime with the L STW instruction, which loads the entire 16-bit status word into ACCU 1; the low byte of ACCU 1 then holds the bits 0-7 (CC 0 in bit 6, RLO in bit 1, etc.).

The /FC First Check Bit

The /FC bit signals whether the next bit-test instruction is the first check in a logic string. The rule is simple:

1. /FC = 1 immediately before the first bit-logic operation of a logic string.
2. /FC = 0 for all subsequent bit-logic operations until the string is terminated.
3. A logic string is terminated by a save, assignment, set, reset, or any instruction that consumes the RLO (for example =, S, R, JC, JCN, JCB, JBI, JNBI).
4. The start of a new network reinitializes /FC to 1.

When /FC = 1, the A instruction does not AND with the existing RLO; it simply loads the addressed bit into the RLO. When /FC = 0, the A instruction ANDs the addressed bit with the existing RLO. This is the mechanism that lets the first instruction of a new network copy a value into the RLO without being masked by whatever the RLO happened to be at the end of the previous network.

A (AND) Instruction Semantics

The instruction A <address> performs the following sequence on the S7-300 CPU:

1. Read the addressed bit (here M 0.0).
2. If /FC = 1, copy the bit value into the RLO and clear /FC. (This is the first check.)
3. If /FC = 0, AND the bit value with the current RLO and store the result back in the RLO.
4. Update the STA bit to reflect the value of the addressed bit.

For A M 0.0 with M 0.0 = 0, the RLO becomes 0 regardless of the prior RLO value, because the first check copies the value. For A M 0.1 with M 0.1 = 1 and a prior RLO of 0, the result of 0 AND 1 is 0, so the RLO remains 0. For A M 0.1 with M 0.1 = 1 and a prior RLO of 1, the result is 1.

JC Jump Conditional Instruction

The instruction JC <label> tests the RLO and acts as follows:

1. If RLO = 1, set /FC = 1 and jump to the label. The RLO is unchanged.
2. If RLO = 0, do not jump. Set the RLO to 1 and continue with the next statement.

The "set RLO to 1 on the no-jump path" is the single most important detail for the source network. After JC L1 is executed without taking the jump, the next instruction starts with RLO = 1, not RLO = 0. This is the precise mechanic that allows the subsequent A M 0.1 to evaluate correctly even if M 0.0 was 0.

Network Boundary RLO Initialization

At the start of every network, the CPU conceptually opens a fresh logic string. The /FC bit is forced to 1, and the RLO is implicitly 0 (it is not loaded into the RLO, because the RLO is only ever written by bit-logic operations). The first A in the network will copy the addressed bit directly into the RLO thanks to /FC = 1. Engineers often ask: "Does the RLO at the start of a network equal the RLO at the end of the previous network?" The answer is: the RLO is not retained across a network boundary in a way that matters for the new network. Because the new network's first instruction uses /FC = 1, the prior RLO is overwritten by the first bit test.

Step-by-Step Trace of the Example Network

With the rules above, trace the network for the precondition stated in the source: M 0.0 = 0 and M 0.1 = 1.

The trace shows the precise answer to the source question: at the start of the network, the RLO is effectively 0 (and /FC is 1). After step 1 the RLO is 0. After step 2 the RLO is 1 (because JC sets it to 1 on the no-jump path). After step 3 the RLO is 1 (because /FC is 1 again, so M 0.1 is copied in directly). After step 4 the program jumps to L2 with RLO = 1.

Case 1: M 0.0 = 0, M 0.1 = 1 (Source Scenario)

This is the scenario from the field report. The execution path is:

1. A M 0.0 sets RLO = 0 because M 0.0 = 0.
2. JC L1 does not jump; it sets RLO = 1.
3. A M 0.1 sees /FC = 1 (because JC opened a new logic string) and copies M 0.1 = 1 into the RLO. RLO = 1.
4. JC L2 takes the jump.

The result is a jump to L2. The common misconception is that after step 1 the RLO is permanently 0, which would prevent the jump to L2. The JC instruction's RLO rewriting on the no-jump path is what makes the network behave as expected.

Case 2: M 0.0 = 1, M 0.1 = 1

1. A M 0.0 sets RLO = 1 because M 0.0 = 1.
2. JC L1 jumps immediately to L1; L2 is never reached.

The RLO is preserved across the jump. The /FC bit is set to 1 at the target label, opening a new logic string for any subsequent A instructions.

Case 3: M 0.0 = 0, M 0.1 = 0

1. A M 0.0 sets RLO = 0.
2. JC L1 does not jump; RLO becomes 1.
3. A M 0.1 sees /FC = 1 and copies M 0.1 = 0 into the RLO. RLO = 0.
4. JC L2 does not jump; RLO becomes 1.

Execution falls through both jumps and continues to the statement after network 1. The final RLO is 1 because JC sets it on the no-jump path.

Verifying RLO in STEP 7

The RLO can be observed in three practical ways on a live S7-300 CPU.

1. STEP 7 STL Monitor (V5.5 / V5.6): Open the block in the SIMATIC Manager editor, switch to STL view, and click the "Monitor" (glasses) icon. The status column on the right of the STL window displays the RLO and STA bits for every statement as the program runs. The column will show "0" or "1" for RLO and STA on the highlighted line.
2. TIA Portal STL Watch: In TIA Portal, open the program block in STL representation and start monitoring. The RLO and status bits are shown in the right-hand status column, identical in meaning to STEP 7.
3. Programming L STW in a watchpoint: Insert L STW; T MW 200 at a safe point in the program and observe MW 200. Bit 1 of MW 200 (mask 0x0002) is the RLO, bit 2 (mask 0x0004) is STA, and bit 8 (mask 0x0100) is BR. This is the most robust way to capture the status word during commissioning without relying on the editor's display logic.

Related Jump Instructions and Their RLO Semantics

JC is one of several conditional jumps in the S7-300 STL set. The RLO handling differs subtly between them, and the wrong choice produces the same kind of confusion as the source question.

JC, JCB, JCN, JNBI, and JMP all force /FC = 1 at the target. JL also opens a new logic string. Note that JC, JCN, JCB, and JNBI all set the RLO to 1 on the no-jump path, which is the only behavior in the S7-300 jump set that depends on whether the jump is taken. This is the property that resolves the source question.

Common Misconceptions and Pitfalls

1. "The RLO at the start of a network equals 1 (like a power rail in LAD)." This is a useful analogy for Ladder Logic, where the left rail is conceptually energized. In STL, the RLO at the start of a network is implicitly 0; the first A instruction writes the addressed bit into the RLO because /FC = 1. The analogy breaks the moment you start reasoning about STL semantics.
2. "After an unsuccessful JC, the RLO is still 0." This is the precise misconception in the field report. After a JC that does not jump, the RLO is 1. The next A instruction will then AND with RLO = 1, or, if /FC was reset to 1 by JC, it will copy the addressed bit directly into the RLO.
3. "JC sets /FC to 0." JC sets /FC to 1 on the no-jump path, opening a new logic string. This is what allows the next A to act as a first check.
4. "M 0.0 = 0 means the whole network does nothing." False. Even with M 0.0 = 0, the JC rewrites the RLO to 1 and execution continues.
5. "A network with only A and JC leaves the RLO at the value of the last A." Generally true only if the last JC is taken. If the last JC is not taken, it sets the RLO to 1, which can cause surprising =, S, or R behavior on the next line.

Best Practices for STL Network Design

1. Avoid writing the RLO on the line immediately after a non-taken JC. If the RLO value at the end of the network matters (for example, for a subsequent =), set the RLO explicitly with SET (RLO := 1) or CLR (RLO := 0) so the intent is obvious.
2. Use SET / CLR at the start of a network to document the initial RLO assumption. Although the first A overwrites the RLO, placing a SET or CLR on its own line makes the logic visible to a reviewer reading STL cold.
3. Always document the /FC boundary. Every A, AN, O, ON, X, XN at the top of a new logic string will overwrite the previous RLO. Add a comment line above such a statement: // new logic string, /FC = 1.
4. Prefer LAD or FBD for production code. The S7-300 supports STL, LAD, and FBD interchangeably for most blocks. LAD and FBD hide the RLO mechanics from the user and avoid the entire class of confusion raised in the source question. STL remains valuable for compact, performance-sensitive, or jump-heavy logic, but it should be a deliberate choice.
5. When converting STL to LAD or FBD, expect restructuring. The S7-300 editor can convert STL to LAD only if the STL is "LAD-representable" (for example, no jumps, no accumulator logic, no L STW). Networks that mix A, JC, and fall-through logic typically convert only partially; the editor will mark the unconvertible portion as a "black box" STL block.

Cross-References and Supporting Documentation

The RLO, /FC, and jump semantics documented in this article are described in detail in the following official Siemens references:

• Siemens: Programming and Operating Manual - Statement List (STL) for S7-300/400
• Siemens: S7-300 CPU 315-2 PN/DP Manual (6ES7315-2EH14-0AB0)
• Siemens: S7-300 Automation System, Module Specifications Reference Manual
• Siemens: STEP 7 V5.6 Programming and Operating Manual
• Siemens SiePortal: S7-300 Learning Resources Entry Point

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