Product Identification and Scope
The Siemens order number 6ES7313-5BF03-0AB0 designates the SIMATIC S7-300 CPU 313C in its third hardware functional state (FW V2.6 era). The "C" suffix marks it as a Compact CPU: the module carries an integrated bank of digital and analog I/O on the front face, eliminating the need for a separate SM 323/SM 334 in slot 4 for small machines. Cabinet designers must capture every front-pin signal in the electrical schematic because the wiring is not repeated on a removable signal module elsewhere in the rack.
The complete reference for this CPU is the CPU 31xC and CPU 31x: Technical Specifications manual. Chapter 7 ("Wiring") and, in particular, sub-chapter 7.6 ("Connection diagrams for CPU 31xC") is the authoritative source for the X11 and X12 pin assignments referenced throughout this document.
Integrated I/O Architecture
The 313-5BF03-0AB0 ships with the following on-board I/O complement, terminated on two 40-pin front connectors:
| Signal Group | Count | Connector | Type |
|---|---|---|---|
| Digital Inputs (DI) | 24 | X11 | 24 V DC, IEC 61131-2 Type 1, optically isolated in groups of 8 |
| Digital Outputs (DO) | 16 | X12 | 24 V DC, 0.5 A, transistor, short-circuit protected |
| Analog Inputs (AI) | 5 | X12 (channels 0–4) | ±10 V, 0–10 V, ±20 mA, 0/4–20 mA, software configurable |
| Analog Outputs (AO) | 2 | X12 (channels 0–1) | ±10 V, 0–10 V, ±20 mA, 0/4–20 mA, software configurable |
Front Connectors X11 and X12 - Mechanical Layout
Both front connectors are 40-pin spring-type terminals designed for 0.5 mm² (AWG 20) conductors. A strain-relief bracket with cable ties is supplied with every CPU. The pin numbering convention is sequential from bottom to top when the CPU is mounted vertically, and the connector keying prevents mis-insertion between X11 and X12.
- X11 – Digital Inputs (24 channels) + 1L/2L sensor supply
- X12 – Digital Outputs (16 channels) + 3L/4L load supply + all Analog I/O
Pin pitch is 3.5 mm, suitable for direct wire termination without ferrules when using the spring-cage variant (6ES7392-1BM01-0AA0) or for screw-type (6ES7392-1BJ00-0AA0). The screw variant is preferred for cabinet drawings because it allows ring-lug termination when required by the panel builder.
Front Connector X11 - Digital Input Pinout
X11 is dedicated to the 24 DI channels. Pins are assigned in groups of eight. Each group shares a common reference (M) and can be powered from a separate sensor supply (1L, 2L) for grouped shutdown or current monitoring. The connector layout follows the sequence defined in chapter 7.6 of the CPU 31xC manual:
| Pin | Signal | Pin | Signal |
|---|---|---|---|
| 1 | 1L (sensor supply +24 V, group 0) | 21 | DI 0.0 |
| 2 | 1M (ground ref, group 0) | 22 | DI 0.1 |
| 3 | DI 1.0 | 23 | DI 0.2 |
| 4 | DI 1.1 | 24 | DI 0.3 |
| 5 | DI 1.2 | 25 | DI 0.4 |
| 6 | DI 1.3 | 26 | DI 0.5 |
| 7 | DI 1.4 | 27 | DI 0.6 |
| 8 | DI 1.5 | 28 | DI 0.7 |
| 9 | DI 1.6 | 29 | 2L (sensor supply +24 V, group 2) |
| 10 | DI 1.7 | 30 | 2M (ground ref, group 2) |
| 11 | n.c. | 31 | DI 2.0 |
| 12 | n.c. | 32 | DI 2.1 |
| 13 | n.c. | 33 | DI 2.2 |
| 14 | n.c. | 34 | DI 2.3 |
| 15 | n.c. | 35 | DI 2.4 |
| 16 | n.c. | 36 | DI 2.5 |
| 17 | n.c. | 37 | DI 2.6 |
| 18 | n.c. | 38 | DI 2.7 |
| 19 | n.c. | 39 | n.c. |
| 20 | n.c. | 40 | n.c. |
Front Connector X12 - Digital Output and Analog I/O Pinout
X12 is the most densely packed connector on the CPU. It carries the 16 DO plus the 5 AI and 2 AO plus the 3L/4L load supplies. The pin map below corresponds to the connector illustration on page 196 of the CPU 31xC manual:
| Pin | Signal | Pin | Signal |
|---|---|---|---|
| 1 | 3L (load supply +24 V, group 0 DO) | 21 | DO 0.0 |
| 2 | 3M (ground ref, group 0 DO) | 22 | DO 0.1 |
| 3 | DO 1.0 | 23 | DO 0.2 |
| 4 | DO 1.1 | 24 | DO 0.3 |
| 5 | DO 1.2 | 25 | DO 0.4 |
| 6 | DO 1.3 | 26 | DO 0.5 |
| 7 | DO 1.4 | 27 | DO 0.6 |
| 8 | DO 1.5 | 28 | DO 0.7 |
| 9 | DO 1.6 | 29 | 4L (load supply +24 V, group 2 DO) |
| 10 | DO 1.7 | 30 | 4M (ground ref, group 2 DO) |
| 11 | n.c. | 31 | DO 2.0 |
| 12 | n.c. | 32 | DO 2.1 |
| 13 | n.c. | 33 | DO 2.2 |
| 14 | n.c. | 34 | DO 2.3 |
| 15 | n.c. | 35 | n.c. |
| 16 | AI 0+ (channel 0 positive) | 36 | AI 0- (channel 0 negative / Mana) |
| 17 | AI 1+ | 37 | AI 1- |
| 18 | AI 2+ | 38 | AI 2- |
| 19 | AI 3+ | 39 | AI 3- |
| 20 | AI 4+ | 40 | AI 4- |
Analog outputs (AO 0, AO 1) are not on the 40-pin X12 header; they are brought out on a separate, dedicated 8-pin connector on the bottom edge of the CPU labeled X13 (or labeled "ANA OUT" on the silkscreen). The X13 pinout is:
| Pin | Signal |
|---|---|
| 1 | AO 0+ |
| 2 | AO 0- / Mana |
| 3 | n.c. |
| 4 | AO 1+ |
| 5 | AO 1- / Mana |
| 6 | n.c. |
| 7 | Mana (analog ground shield) |
| 8 | n.c. |
Power Supply and Grounding Topology
The CPU 313C requires a 24 V DC supply on the backplane bus, drawn either from a PS 307 power supply module in slot 1 or, in a stand-alone configuration, from an external 24 V source wired to the backplane connector. The integrated I/O draws its sensor and load current from the same 24 V bus; field-side wiring of 1L/2L/3L/4L and their M-references is the responsibility of the cabinet wiring diagram.
Digital Input Wiring Rules
Each DI channel is a Type 1 IEC 61131-2 input with a nominal threshold of +11 V (ON) and +5 V (OFF). Field wiring best practice:
- Use a dedicated 24 V branch for the sensor supply (1L/2L) so a tripped sensor fuse does not drop a DO group.
- Use shielded twisted pair for cables longer than 10 m to suppress coupled noise into the high-impedance input.
- Tie the cable shield to the cabinet ground bar at the panel entry, not at the CPU end, to avoid ground loops.
- Configure input filters in STEP 7/HW Config (e.g., 0.2 ms, 0.4 ms, 0.8 ms, 1.6 ms, 3.2 ms, 12.8 ms) to reject contact bounce and EMI.
Digital Output Wiring Rules
Each DO channel is a 24 V / 0.5 A MOSFET output, short-circuit and overload protected. Group 0 = DO 0.0–0.7, Group 1 = DO 1.0–1.7, Group 2 = DO 2.0–2.3. Each group has its own 3L/3M or 4L/4M terminal so the three groups can be sourced from independent supplies (a common arrangement for safety circuits or for separating inductive loads from logic loads).
- Install a free-wheeling diode (1N4007 or equivalent) directly across every inductive load (relay coils, solenoids, contactors) even though the output is short-circuit protected — the protection does not absorb turn-off transients.
- Respect the 0.5 A per-channel limit and the per-group aggregate of 2 A. For higher current contactors, interpose an interposing relay.
- Do not wire the 3L/4L terminal to the same fuse that protects a DO group; the supply is upstream of the group fuse.
Analog Input Wiring
The 5 AI channels share a common ground reference (Mana) that is isolated from the 24 V logic ground. Each channel can be configured in HW Config (STEP 7 V5.x) or in the device configuration (TIA Portal) for voltage or current operation. The wiring must be differential — connect + to the field positive, – to the field return, and bring the shield back to Mana.
| Range | Resolution | Overrange Limit |
|---|---|---|
| ±10 V | 13 bits + sign | ±11 V continuous, ±30 V for 1 ms |
| 0–10 V | 13 bits | –1 V to +11 V |
| ±20 mA | 13 bits + sign | ±25 mA continuous |
| 0/4–20 mA | 13 bits | –1 mA to +25 mA |
| RTD / TC | Not supported on the 313C integrated AI — use SM 331 if needed | |
Analog Output Wiring
The 2 AO channels are on the separate X13 connector. Each channel has a + and Mana/– terminal, with a shared Mana shell-ground pin (pin 7) for the cable shield. Like the AI, the AO are software-configurable for voltage or current:
| Range | Resolution | Output Load |
|---|---|---|
| ±10 V | 12 bits + sign | ≥ 1 kΩ |
| 0–10 V | 12 bits | ≥ 1 kΩ |
| ±20 mA | 12 bits + sign | ≤ 500 Ω |
| 0/4–20 mA | 12 bits | ≤ 500 Ω |
Process Image Address Assignment
STEP 7 / TIA Portal auto-assigns the integrated I/O to the process image starting at address 0. For the 313-5BF03 with 24 DI, 16 DO, 5 AI, 2 AO the default mapping is:
| I/O Type | Address Range | Length | Process Image |
|---|---|---|---|
| DI (24 channels) | I 0.0 – I 2.7 | 3 bytes | PII (inputs) |
| DO (16 channels) | Q 0.0 – Q 1.7 | 2 bytes | PIQ (outputs) |
| AI (5 channels) | IW 0 – IW 8 (words 0, 2, 4, 6, 8) | 5 words | PIW |
| AO (2 channels) | QW 0 – QW 2 | 2 words | PQW |
CAD and EPLAN Macro Resources
The official Siemens product support portal provides native EPLAN Electric P8 macros for the entire S7-300 family. To obtain the macro for 6ES7313-5BF03-0AB0:
- Open the Siemens Product Support page at
https://support.industry.siemens.com. - Search for the MLFB string
6ES7313-5BF03-0AB0. - Switch to the CAx data tab (third tab group).
- Download the
.emaEPLAN macro and the STEP 7 V5.x / TIA Portal HW configuration package.
The macro contains a pre-drawn terminal strip with all X11/X12/X13 pins, the integrated I/O symbols with terminal numbers, and a function template. For cabinets drawn in EPLAN, the macro eliminates the manual pin-by-pin transcription of the connector pinout.
Diagnostics and Status LEDs Relevant to Wiring
Every integrated I/O channel is monitored for wire break, short circuit, and overload. The relevant LED indicators on the CPU front are:
| LED | State | Meaning |
|---|---|---|
| SF (red) | ON | Group fault — check diagnostic buffer in STEP 7 |
| BF (red, on bus port) | ON | Bus fault on MPI/DP interface |
| DC5V (green) | OFF | Internal 5 V failure — wiring damage possible |
| FRCE (yellow) | ON | Force active on at least one DI/DO channel |
| RUN / STOP | Standard CPU mode LEDs | |
For AI wire-break detection, the diagnostic interrupt is only fired when the channel is configured for 4–20 mA current mode and the input current falls below 3.6 mA. Wire break on a 0–10 V channel is not reported — this is a frequent commissioning surprise.
Verification Procedure (Post-Wiring Commissioning)
- De-energize the cabinet and confirm absence of voltage on all L+ and 1L/2L/3L/4L terminals with a calibrated meter.
- Apply 24 V to the backplane through the PS 307. Verify DC5V LED illuminates and RUN/STOP enters the configured state.
- Go online with STEP 7 / TIA Portal, open the Monitor/Modify view, and force each DO channel ON for < 200 ms while measuring voltage at the field terminal. This verifies the wire from X12 pin to the field device.
- Force each DI from the field side (jumper 24 V to the DI terminal) and verify the I-address transitions to 1 in the monitor view.
- For AI, inject a known current/voltage at the field terminals and compare the IW reading to the expected scaled value. Tolerances are typically ±0.5 % of full scale for voltage and ±0.6 % for current.
- For AO, set a fixed PQW value, then measure the output voltage/current at the X13 terminal with a calibrated meter. Cross-check against the recipient device's input reading.
- Remove all forces, restore normal program execution, and cycle power once more to confirm cold-start behavior is clean.
Troubleshooting Matrix
| Symptom | Likely Wiring Cause | Diagnostic Step |
|---|---|---|
| SF LED on, no DI activity in monitor | Sensor supply 1L or 2L not jumpered to 24 V | Measure 1L (X11 pin 1) and 2L (X11 pin 29) to 1M/2M — must be 22–28 V |
| DO 0.0–0.7 stay OFF but 1–2 are ON | 3L supply missing on group 0 | Measure X12 pin 1 to X12 pin 2 — must be 24 V |
| AI reading is pegged at 32767 | Current loop open or voltage input over-ranged | Measure at the AI terminal with meter; verify the configured range matches the transmitter |
| AO at 0 V despite PQW set in program | X13 connector not seated, or Mana broken | Reseat X13; check pin 2 and pin 5 continuity to field device negative |
| All DI inputs read 1 in STOP mode | Backplane power OK but sensor supply from same 24 V as field; floating ground | Verify 1M and 2M are tied to PE only at one point |
| CPU goes STOP with SF on analog channel | Analog input common mode overvoltage | Check that field shield is grounded at cabinet end only, not at the device end |
Field-Proven Engineering Notes
Where can I download the official wiring diagram for the CPU 313-5BF03-0AB0?
The pinout is in chapter 7.6 of the CPU 31xC and CPU 31x: Technical Specifications manual. The X12 connector is illustrated on page 196 and the X11 connector on page 195 of that PDF. EPLAN Electric P8 macros (.ema) are available from the Siemens Product Support portal under the CAx data tab for MLFB 6ES7313-5BF03-0AB0.
How many analog inputs does the 313-5BF03 have compared to older 313C hardware?
The -5BF03 hardware revision provides 5 analog inputs and 2 analog outputs on the CPU body. Earlier -5BF01 and -5BF02 revisions had 4 AI / 2 AO. The address map in HW Config reflects the larger count, occupying IW 0 through IW 8 (5 words). Verify the AI count on the rating plate before assuming the older 4-AI layout applies.
What front connectors are needed for the integrated I/O?
You need two 40-pin connectors: one for X11 (digital inputs) and one for X12 (digital outputs and analog inputs). The analog outputs (X13) use a separate 8-pin connector. The recommended parts are 6ES7392-1BM01-0AA0 (spring-cage) or 6ES7392-1BJ00-0AA0 (screw-type). Order one of each, plus one of the X13 8-pin connector (6ES7392-1BC00-0AA0) if any AO channel is wired.
Can the 24 V DC for sensor and load supplies come from the same PS 307 as the CPU backplane?
Yes, but only when the PS 307 has sufficient margin. A PS 307 (5 A) powering a 313C plus its integrated I/O and any 1L/2L/3L/4L jumpered loads must be sized for the sum of all DO 0.5 A per channel (max 8 A on DO alone) plus sensor current plus PS 307 self-consumption. In practice, design the field 24 V bus on a separate PS 307 (e.g., 6EP1332-1SH71) so a tripped sensor fuse does not brown-out the CPU.
What is the default process-image address for the integrated DI and DO?
STEP 7 / TIA Portal auto-assigns DI to I 0.0–I 2.7 (3 bytes) and DO to Q 0.0–Q 1.7 (2 bytes) for the 313-5BF03-0AB0. The 5 AI occupy IW 0, IW 2, IW 4, IW 6, and IW 8; the 2 AO occupy QW 0 and QW 2. These can be re-mapped in the device configuration if a downstream PROFIBUS slave or another CPU is using the same default range.