Siemens LOGO! Asynchronous Pulse Generator Drift: Sync Fix

Problem Definition: Asynchronous Pulse Generator Drift in LOGO!

Siemens LOGO! soft-PLC programs frequently require two periodic signals whose frequencies are related by a fixed ratio — for example a 1 Hz and a 0.5 Hz clock driving sequential pump stages, alternated indicator lamps, or staged heating zones. The natural implementation places two Asynchronous Pulse Generator blocks side by side, one with TH = 00:05:00 (TL = 00:00:00) and another with TH = 00:10:00 (TL = 00:00:00). The intent is a perfect 2:1 frequency relationship.

The result in LOGO!Soft Comfort simulation, and to a lesser degree on real hardware, is that the two clocks drift. Within a few cycles the cumulative lag becomes visible on the on-screen counter: one block reads 01:51 while the other reads 01:54; over hours the offset grows without bound. This drift is not a defect in the function block — it is the expected behavior of any two free-running oscillators whose periods are not exactly phase-locked to a common time base.

The drift has two components:

1. Quantization of TH and TL values to the LOGO! time base (10 ms on LOGO! 8 / 0BA7-0BA8, 100 ms on LOGO! 0BA5-0BA6).
2. Independent counters for each block; even when periods are mathematically integer multiples, scan-to-scan jitter is uncorrelated, so a single ±1 tick offset on one block never self-corrects.

Root Cause: Why Two Independent Counters Cannot Stay Locked

Each asynchronous pulse generator in LOGO! is implemented internally as a pair of independent counters, one for TH and one for TL. At every controller scan, both counters decrement by the elapsed time delta (capped at the LOGO! scan cycle). When the TH counter reaches zero, the output transitions and the TL counter begins. When the TL counter reaches zero, the output transitions back and TH starts again.

For two blocks A and B both running on the same scan, phase lock reduces to a simple integer relationship:

T_A × N = T_B × M where N, M are positive integers

If N and M are coprime integers with no quantization error, the two blocks repeat their joint state every T_A × N seconds. In our example, T_A = 5 s, T_B = 10 s, N = 2, M = 1 — exact integer ratio, in theory no drift. But because the LOGO! stores TH and TL as separate quantized values, any rounding error in one block propagates and never cancels.

When a programmer enters 00:05:01 for block A and 00:10:01 for block B, the actual stored values are 301 s and 601 s. Two periods of A equal 602 s, which is 1 s longer than one period of B. Every two cycles of A, B leads by 1 s; the lag accumulates in proportion to the rounding residual.

Quantization Residual Calculation

For a LOGO! 8 (0BA7/0BA8) controller with a 10 ms time base, the stored tick value is:

ticks = round(seconds × 100)

The residual error per period equals:

e = ticks × 0.01 s - displayed_seconds

LOGO! Asynchronous Pulse Generator Block Reference

The asynchronous pulse generator is a special function block available in the LOGO!Soft Comfort function block diagram (FBD) library. Per the Siemens Industry Online Support entry ID 109741041 — Asynchronous pulse generator, the block exposes three configurable parameters:

The effective period of the block is:

T = TH + TL

The output duty cycle is:

D = TH / (TH + TL)

When TH ≥ TL, the output is HIGH for TH then LOW for TL on every period. When TL = 0, the output is HIGH for TH only and never returns LOW; the block behaves as a one-shot trigger rather than an oscillator. To produce a true periodic clock with a 50% duty cycle, set TH = TL with both equal to half the desired period.

Solution 1: Period Re-Parameterization for Mathematical Alignment

The first mitigation adjusts the two blocks so their periods satisfy 2 × T_A = T_B exactly, with values that round to integer tick counts on both controllers:

1. Block A: TH = 00:05:00, TL = 00:00:00 → T_A = 5.000 s (500 × 10 ms)
2. Block B: TH = 00:10:00, TL = 00:00:00 → T_B = 10.000 s (1000 × 10 ms)

This eliminates quantization error entirely. Both blocks have exact integer tick counts, so any per-scan jitter is bounded by one tick (10 ms on LOGO! 8) and does not accumulate.

For applications where the on-screen counter must show a non-zero minutes portion (for visual debugging), a tuning variant is acceptable and reproduces the field-tested configuration:

1. Block A: TH = 00:05:01, TL = 00:00:00 → T_A = 301 s
2. Block B: TH = 00:10:01, TL = 00:00:01 → T_B = 602 s = 2 × 301 s

The two periods are exact integer multiples, so the joint state repeats every 602 s with no phase slip. This is the configuration that has been field-verified to keep the two counters aligned.

Solution 2: Synchronous Clocks via Pulse Relay (1:2 and 1:4 Ratios)

For 1:2 and 1:4 frequency division, the canonical Siemens approach is one master async pulse generator feeding one or more pulse relays (RS bistable function blocks). The pulse relay toggles its output on every rising edge of its input, halving the input frequency. Stacking two relays produces 1:4 division from the same master.

Wiring (FBD)

1. Master async pulse generator (BF block):
   • TH = 00:00:01 (1 s HIGH)
   • TL = 00:00:01 (1 s LOW)
   • Output period: 2 s, duty 50%
2. Pulse relay 1 (RS block):
   • S input = master output
   • R input = logic LOW (constant 0)
   • Q output toggles every 2 s, period 4 s
3. Pulse relay 2 (RS block, optional for 1:4):
   • S input = relay 1 output
   • R input = logic LOW
   • Q output toggles every 4 s, period 8 s

Because every output is derived from the same master counter, no drift is possible — the relationship is mathematically locked regardless of scan jitter.

SVG Timing Diagram

Solution 3: Counter-Based Divider for Arbitrary Ratios

For division ratios other than powers of two (1:3, 1:5, 1:7, 1:N), use the up/down counter (CUF block) or a threshold counter. The master clock drives the count input, and the counter resets on threshold, producing an output pulse every N input pulses.

Implementation Pattern

1. Master async pulse generator: TH = TL = 00:00:00.5 → 1 Hz output (period 1 s)
2. Up/down counter (CUF):
   • Count input = master output rising edges
   • On-threshold = N − 1 (for example 2 for 1:3 ratio)
   • Reset input = comparator output (counter ≥ N)
   • Output Q = HIGH when counter reaches threshold
3. The Q output pulses once every N master cycles.

This pattern scales to any positive integer divisor and preserves phase lock because every output edge is tied to a master edge.

LLD (Ladder Logic) Code Equivalent

|     Master      |      |      Counter      |
|  Async Pulse    |      |     CUF block     |
|  (TH=0.5s,      |----->|  Cnt=0, On=N-1    |
|   TL=0.5s)      |      |  Reset <- Qn      |
|                 |      |  Q --> Output      |
+-----------------+      +-------------------+

Hardware Behavior vs Simulation Behavior

The Siemens LOGO! scan cycle characteristics by generation:

On real hardware, the deterministic scan keeps two independent counters in phase to within ±1 scan tick. Drift between them is bounded, not cumulative. In LOGO!Soft Comfort simulation, the per-scan order in which blocks are evaluated is fixed by the FBD layout, but simulation jitter (caused by the host PC's thread scheduling) can be 10-100× worse than the hardware scan. This produces a visible drift in simulation that does not appear on hardware. Always verify timing behavior on the actual installed controller.

Implementation: FBD and LLD Equivalents

The asynchronous pulse generator is a special function block; in FBD it appears as a single BF block. In LLD (ladder logic) the equivalent is constructed from:

• An on-delay timer (T_ON) for the TH phase
• An off-delay timer (T_OF) for the TL phase
• A latching relay (RS block) or equivalent flip-flop for the output

The pattern:

     +----[T_ON : TH]----+        +----+
IN --|                   |--------|    |
     +----[T_OF : TL]----+        | RS |-- Q out
                                +---|    |
                                    +----+

When IN rises, T_ON begins timing TH. After TH expires, T_ON's output sets RS. T_OF begins when IN falls; when T_OF expires (TL), RS resets and the cycle can restart. The output Q is HIGH for TH, LOW for TL, repeating as long as IN is held HIGH.

Timing Diagram: Drift Visualization

The shifted transitions on the third trace show the lag introduced when the second block's period is not an exact multiple of the first. Over hours, the third trace continues to slide right relative to the second trace.

Edge Cases and Field Caveats

1. Power-on reset behavior. All async pulse generators initialize to a known state (output LOW) at power-on. If two blocks must be phase-aligned at start-up, configure both with identical TH/TL values and accept that the first period includes the boot delay.
2. Scan overrun. If the LOGO! scan is interrupted (for example by a long web-server request on a LOGO! 8 with network access), one or more blocks can lose ticks. This appears as a single-shot phase jump, not a sustained drift.
3. Retentivity. By default, async pulse generators are retentive. Their counter value survives a power-cycle, so the joint state at restart may not match the joint state at last power-down.
4. Maximum block count. A LOGO! 8 supports up to 400 function blocks; if you are dividing many stages from one master, verify headroom.
5. Input Inv behavior. The Inv input only flips output polarity; TH and TL are not affected. Using Inv on a master block inverts all downstream derived signals.
6. Time format. The editor display format defaults to minutes:seconds. Switch to h:mm:ss.t for sub-second precision when entering periods under 60 s.

Verification Checklist

1. Confirm TH and TL values round to integer tick counts on the target controller's time base (10 ms on LOGO! 8, 100 ms on LOGO! 6/7).
2. Verify 2 × T_A = T_B (or N × T_A = M × T_B) at the tick level, not the displayed level.
3. Capture both outputs on a logic analyzer or scope for at least 100 cycles and confirm zero relative drift.
4. Test on the actual installed LOGO! hardware, not only in LOGO!Soft Comfort simulation.
5. If using pulse-relay or counter-based division, verify the master async pulse generator is the only timing source — no other blocks should use independent timers.
6. Confirm power-on state of all derived signals matches the expected sequence; disable retentivity on the master if deterministic restart is required.
7. Confirm TH ≥ 2 × scan_cycle to prevent the block from updating twice within a single scan.

Frequently Asked Questions