Siemens LOGO! Priority-Based Sequential Coil Control with SR Flip-Flop

A field-engineering recipe for driving four mutually-exclusive coils on a Siemens LOGO! 8 logic module where multiple "switch-on" inputs can be asserted simultaneously. The solution uses one SR (set/reset) flip-flop per coil, an enable bit per output, and a cascaded on-delay timer chain acting as a sequencer. Priority is hard-wired by index: the lowest-numbered active input wins, runs for a fixed interval, and then the next active input takes over. The pattern eliminates the common "no coil energizes when two inputs overlap" failure mode caused by unconstrained set races on a shared SR flip-flop.

1. Problem Statement: Why a Bare SR Flip-Flop Fails with Multiple Active Inputs

The original control requirement is straightforward on the surface:

• 4 digital outputs, call them Q1, Q2, Q3, Q4, drive 4 coils through interposing relays.
• 8 digital inputs: I1, I2, I3, I4 are "switch-on" commands; I5, I6, I7, I8 are "switch-off" commands.
• Each output has its own SR flip-flop: SR_k.Set = I_k, SR_k.Reset = I_(k+4).
• Only one coil can be energized at any given time (mutual exclusion).
• If a "switch-on" input is asserted, that coil takes priority over any other.

The naive implementation has a single defect: if more than one "switch-on" input is active simultaneously, the mutual-exclusion constraint is not enforced, and the user typically observes that no coil energizes. The root cause is that the four SR flip-flops can be set independently with no arbitration, so the LOGO! solves them in a sequence dictated by block order, and the auxiliary contact on Q_k is missing — there is no "previous coil is OFF" condition in any of the four set equations.

The fix is to introduce a sequencer that walks the program through Q1 → Q2 → Q3 → Q4 on a fixed time base, and an enable bit per output that becomes true only when the sequencer is parked on that slot and the corresponding "switch-on" input is asserted.

2. Hardware and Software Prerequisites

Reference the Siemens LOGO! product page and the LOGO! 8 system manual on the Siemens Industry Online Support portal for hardware revisions and approved expansion modules.

3. Functional Requirements (Rewritten Spec)

Before writing a single FBD block, restate the requirement as a deterministic algorithm. The behavioral spec becomes:

1. Continuously scan the four "switch-on" inputs (I1, I2, I3, I4).
2. Maintain a 4-state sequencer that visits slots {1, 2, 3, 4} in order, dwelling T_dwell seconds in each slot.
3. When the sequencer is in slot k AND I_k is asserted, set the SR flip-flop that drives Q_k.
4. When the sequencer leaves slot k (transitions to k+1, or wraps from 4 to 1) OR I_(k+4) is asserted, reset the SR flip-flop for Q_k.
5. Wraparound: after slot 4, the sequencer returns to slot 1; any inputs that re-asserted after their last visit are re-detected.

This spec guarantees mutual exclusion (only one slot is active at a time) and the "lowest number wins" priority property (the sequencer visits 1 before 2, 2 before 3, etc.).

4. Architecture Overview

The solution has four functional islands connected by a shared sequencer bus.

Figure 1 — Functional islands: inputs, enable AND, SR latch, sequencer bus, and outputs.

5. Step 1 — Input/Output Assignment and Naming

Open LOGO! Soft Comfort and create a new program. Set the target device to the correct LOGO! 8 base module (this determines which blocks are available). Reserve the following symbolic names in the I/O name table:

Use meaningful names. LOGO! Soft Comfort V8.3+ allows up to 12 characters per I/O name. Keeping the prefixes ON_ and OFF_ in the name makes the FBD self-documenting.

6. Step 2 — Build the SR Flip-Flop Foundation (One Per Coil)

Drop four SR latching relays (block class "Latching relay", icon with S and R pins) on the FBD canvas. Wire them as follows:

• SR_1.Set ← EN_1 (enable bit, defined next section)
• SR_1.Reset ← OFF_1 OR SEQ_NEXT_1 (sequencer is about to leave slot 1)
• SR_1 output → Q1

Repeat the same pattern for SR_2, SR_3, SR_4, incrementing both the input index and the sequencer slot. In LOGO! Soft Comfort, the SR block is found under "Special functions → Latching relay → SR (set/reset with set priority)" or the equivalent menu path. The "set priority" variant (also called RS flip-flop in some locales) is not what we want here — use the SR variant with set dominant, so an asynchronous reset cannot de-energize a coil mid-run unless OFF_k is asserted.

7. Step 3 — The Enable Bit

The enable bit is the keystone of the entire pattern. For each coil k:

EN_k = SEQ_k AND ON_k

where SEQ_k is a Boolean flag that is true only while the sequencer is dwelling in slot k. Build it with an AND block (block class "Basic functions → AND"):

1. Drop an AND gate on the canvas.
2. Wire input 1 to SEQ_k (the sequencer bit, built in Step 4).
3. Wire input 2 to ON_k (the I1–I4 input).
4. Output is the enable bit EN_k, which feeds the SR_k.Set pin.

With this gate, a coil can only be latched when both conditions are met: (a) the operator has asked for that specific coil, and (b) it is the sequencer's turn to honor that request. If ON_k is asserted while the sequencer is in any other slot, nothing happens — the request is "queued" by the persistent ON_k input and will be picked up on the next pass.

8. Step 4 — Sequencer Implementation with a Timer Chain

LOGO! 8 has no native "ring counter" block, but a four-stage sequencer is trivial to build from on-delay timers (block class "Special functions → Timers → On-delay") chained together, with a clock generator providing the advance pulse.

8.1 Clock pulse generator

Use an asynchronous pulse generator (block B14) with a 50% duty cycle at the desired dwell frequency. For example, if you want a 5-second dwell per coil, configure it for a 2.5 s on / 2.5 s off cycle. Name the output TICK.

8.2 Four-stage ring counter

Chain four on-delay timers such that each timer triggers the next, and only one is timing at any given time:

TICK ─► TMR1 (Ta = 5 s) ─► SEQ_1 = 1 while timing
                    └─► TMR2 (Ta = 5 s) ─► SEQ_2 = 1 while timing
                                        └─► TMR3 (Ta = 5 s) ─► SEQ_3 = 1 while timing
                                                            └─► TMR4 (Ta = 5 s) ─► SEQ_4 = 1 while timing
                                                                                └─► (back to TMR1)

In LOGO! Soft Comfort, this is implemented with four On-delay blocks (B08). The first timer's trigger is the TICK edge; the second's trigger is the first timer's output's falling edge (use a NOT + edge-detect or simply wire the negated output back). The pattern repeats. Each timer's output Q becomes the SEQ_k flag.

8.3 Alternative: counter + decoder

For finer control, replace the timer chain with a single up/down counter (B19) and four analog comparators (B27). The counter increments on each TICK; each comparator asserts when the count matches k. This variant uses fewer timer blocks but is harder to read at a glance.

9. Step 5 — Complete FBD Wiring

The full FBD has 4 SR blocks, 4 AND blocks (one per enable), 1 pulse generator, 4 on-delay timers, 4 OR blocks (one per reset), and a handful of edge/not blocks. A working block count of ~25 fits comfortably in the 400-block budget of a LOGO! 8 base module.

The "NEXT_k" signal is the leading edge of the next sequencer slot. In the simplest form, NEXT_1 = SEQ_2, NEXT_2 = SEQ_3, etc., with NEXT_4 = SEQ_1 (wrap-around). The OR on the Reset pin ensures the coil drops as soon as the sequencer advances past it, even if OFF_k is never asserted.

10. State Machine Equivalent

The behavior maps cleanly to a four-state Mealy machine. Documenting the state table in the FBD header (as a comment block in LOGO! Soft Comfort) helps the next maintainer.

Priority-by-index falls out automatically: state S0 is always visited before S1, S1 before S2, S2 before S3. The "all coils have run" requirement from the original spec is interpreted as "the sequencer makes one full revolution".

11. Timing Diagram

Figure 2 — Sequencer waveform. Q1 follows SEQ_1; Q2 follows SEQ_2; coils OFF when their sequencer slot is not active.

12. Commissioning Procedure

1. Download the program to the LOGO! 8 base module via Ethernet. Use LOGO! Soft Comfort's "PC → LOGO!" transfer; set the access password if the installation requires it.
2. Switch to RUN mode on the LOGO! display (ESC → Start) or via the online view in Soft Comfort.
3. Online monitor — open the "Online → Monitor on" view. Each wire should now show a live Boolean state (red = 0, blue = 1). Verify TICK is pulsing at the expected rate by watching the pulse generator block.
4. Verify the sequencer — confirm SEQ_1 → SEQ_2 → SEQ_3 → SEQ_4 → SEQ_1 in sequence, each high for 5 s, no overlaps, no gaps.
5. Single-input test — apply only I1. Expect Q1 to energize whenever SEQ_1 is high (every 20 s, for 5 s). Q2, Q3, Q4 stay de-energized.
6. Multi-input test — apply I1 and I2 simultaneously. Expect Q1 to energize during slot 1, Q2 to energize during slot 2, no overlap, no all-off dead time.
7. Off-input test — with Q1 energized (slot 1 active, ON_1 = 1), press I5 (OFF_1). Expect Q1 to drop within one scan, then re-energize when the next SEQ_1 pulse arrives (since ON_1 is still high).
8. Wrap-around test — with all four ON inputs active, run a full 20 s cycle and confirm Q1 → Q2 → Q3 → Q4 fired in order.

13. Edge Cases and Field Notes

13.1 Operator presses "OFF" mid-dwell

The OR gate on the Reset pin ensures that OFF_k clears SR_k immediately, regardless of sequencer state. On the next pass through slot k, if ON_k is still asserted, the coil re-energizes. This matches operator expectations of a "cancel and re-request" interaction.

13.2 Operator presses "ON" then changes their mind

To stop a request entirely, the operator should drop ON_k and assert OFF_k (or just drop ON_k and let the sequencer pass — the next state will not honor the dropped request because the enable bit will evaluate false). Either approach is safe.

13.3 Stuck-on input (failed sensor)

If ON_k latches mechanically high, the corresponding coil will fire on every pass through slot k. The OFF_k input can be used as a maintenance override. A future enhancement is a "max cycles per minute" watchdog using a counter block to detect runaway requests.

13.4 Different dwell times per coil

Replace the four identical on-delay timers with four independently-configured timers, each with its own Ta. The sequencer chain still works because the next stage is triggered on the previous timer's expired output, not on a fixed clock.

13.5 Migrating to a S7-1200/1500

The same enable-bit + sequencer pattern ports to a Siemens S7-1200 using a single FB with a static "slot" variable and four output bits. On TIA Portal, the SR block is replaced with a SET/ RESET coil pair inside an FB, and the sequencer becomes a CASE structure on the slot counter. Reference the TIA Portal help portal for FB templates.

13.6 Memory retention after power cycle

The current implementation loses all sequencer state on power cycle. For applications where the sequence must survive a brown-out, mark the sequencer variables and the SR flip-flops as "retentive" in the block properties. Retentivity is enabled per-block in the Soft Comfort property sheet.

14. Troubleshooting Matrix

15. Sizing the Output Relays (When to Add a Contactors Layer)

LOGO! 8 onboard relay outputs are rated 10 A resistive / 2 A inductive at 250 V AC, with a mechanical endurance of 10 million cycles. For inductive DC coil loads (solenoid valves, contactor coils), always derate by 50% and add a flyback diode directly across the coil. For three-phase motor contactors driven by Q1–Q4, the LOGO! outputs only handle the contactor coil; the main power path is closed by the contactor's main contacts, which must be sized per the motor's full-load current. If the source single-phase FLA is not stated, label the assumption explicitly: a 360 A figure interpreted as three-phase line current gives kVA = √3 × V_LL × I / 1000; the same figure as single-phase gives kVA = V × I / 1000. Do not present one interpretation as fact without stating the assumption.

16. Verification Checklist (Print and Sign Off)

• ☐ TICK pulses visible in online monitor at 5 s ± 5%
• ☐ SEQ_1, SEQ_2, SEQ_3, SEQ_4 each high for 5 s ± 5% in sequence
• ☐ Q1 energizes for 5 s when only I1 active
• ☐ Q2 energizes for 5 s when only I2 active
• ☐ Q3 energizes for 5 s when only I3 active
• ☐ Q4 energizes for 5 s when only I4 active
• ☐ With I1 and I2 both active, Q1 and Q2 alternate with no overlap
• ☐ With all four ON inputs active, full 20 s cycle: Q1 → Q2 → Q3 → Q4 → repeat
• ☐ OFF_1 input drops Q1 within one scan
• ☐ After power cycle, sequencer restarts at SEQ_1 (or resumes if retentive)

17. References Inside the Soft Comfort Project

Add a text comment block at the top of the FBD with the program name, author, date, and revision. LOGO! Soft Comfort allows free-text comments on the FBD canvas. A typical header:

// Program:  PRIORITY_SEQ_v1
// Target:   LOGO! 8 230RCE (6ED1052-1MD08-0BA1)
// Author:   <engineer name>
// Date:     2025
// Rev:      1.0
// Purpose:  Run 4 coils with lowest-numbered-active priority,
//           timed dwell per coil, no concurrent energization.
// Inputs:   I1-I4 = ON requests, I5-I8 = OFF requests
// Outputs:  Q1-Q4 = coil drivers
// Params:   T_dwell = 5.0 s (set on each on-delay timer)
// Notes:    Set-priority SR used. Retentivity OFF for SR blocks.

18. Closing Notes

The enable-bit + sequencer pattern is reusable beyond this four-coil example. It scales to 8 outputs on a LOGO! 8 by extending the timer chain (or moving to a counter + comparator decoder), and the same architecture can be coded in SCL on a S7-1200/1500 with a single function block. The fundamental insight is the same in either platform: priority + dwell time + mutual exclusion cannot be solved with bare combinatorial latches; an explicit scheduler is required.