Siemens LOGO! Soft Comfort: Implementing OR Logic in LAD and FBD

Overview

Siemens LOGO! Soft Comfort (LSC) is the configuration and programming software for the LOGO! 8 logic module family (LOGO! 8.1, 8.2, 8.3, 8.4 and the BM (Basic Module) hardware revisions 0BA8 through 0BA8.Standard). LSC supports the four IEC 61131-3 graphical and textual languages, but on the LOGO! target the editor that matters day-to-day is Ladder Diagram (LAD). FBD (Function Block Diagram) is the alternate graphical mode used when the user wants block-style logic without the ladder rail/coil structure.

The most common first-time frustration with LSC is attempting to wire two normally open (NO) contacts in parallel to drive a coil. LSC rejects this with the message "The output of a contact may only be connected to the next input of a contact or to a coil in the line of the network." The constraint is not a programming error on the user's side - it is a hard rule of the LAD editor's signal-flow model. This article walks through the rule, the correct procedure to build an OR network in LAD, and the FBD alternative that is usually the cleaner solution.

The LAD Editor Rule: One Output, One Path

LAD in LSC is implemented strictly as an IEC 61131-3 ladder network. Each rung has a left power rail (L) and a right power rail (L'). The editor enforces a topological rule:

• Any horizontal element has exactly one output terminal.
• That output terminal may connect to: (a) the next contact's input terminal, or (b) a coil.
• A contact output may NOT split into two parallel branches in the editor UI. The editor will not draw two lines out of a single output pin.

This is why a naive attempt to insert a second NO contact to the left of a coil that already has a contact produces a fault. The user is effectively asking the editor to draw two wires out of one pin, which is illegal in ladder semantics. LSC does not auto-create a "virtual node" or bridge; it requires the user to build the OR using the language primitives that the editor exposes.

Procedure: Building OR Logic in LAD

To wire two NO inputs I1 and I2 to coil Q1 with OR semantics, follow this sequence in LSC V8.x:

1. Open the circuit diagram, place a normally open contact block on rung 1 and assign it input I1.
2. Click to the right of that contact. The cursor must sit on a valid connection point; do not click between two existing pins.
3. Insert a second normally open contact in series on the same rung. Assign it input I2. The network is now I1 AND I2.
4. To convert AND to OR, select the second contact, right-click and choose Convert to OR (or use the menu Edit → Convert → OR). LSC will reflow the rung so the second contact branches above or below the first, with both branches terminating at the same coil terminal.
5. Insert the coil Q1 at the right-hand rail.
6. Compile with F5. The status bar should report 0 errors, 0 warnings.

If the editor refuses to insert a contact at the chosen position, delete the partial rung, start a fresh rung, and rebuild it using the sequence above. Forcing contacts into an existing rung by drag-and-drop often produces the "connect two outputs" fault.

Procedure: Building OR Logic in FBD

FBD in LSC uses standard logic-gate primitives. The OR function is block B001 in the GF (General Functions) constant library. The negated OR is B002; the dual-edge OR is B012.

1. Open the FBD editor.
2. From the GF list, drag block B001 (OR) onto the workspace.
3. Click the upper input pin, draw a wire to input I1, click the lower pin, wire to I2.
4. Click the output pin, wire to coil Q1 (in FBD the output is an assignment block, e.g. Q1 :=).
5. Compile (F5) and simulate (Ctrl+F3).

FBD never raises the "connect two outputs" error because its signal model is many-to-many: any pin may fan out to as many destinations as needed, and any input may accept any number of source wires through the implicit OR of the pin (the editor draws a dot for the wired-OR connection point).

LAD vs FBD Comparison Table

Known LSC Editor Bugs Affecting LAD

The LOGO! community has reported the following recurring defects, most of them on LSC V7.x and V8.0 through V8.2 with 0BA8.Standard hardware. They are documented here as operational risk; users on the latest LSC service pack should verify each item against their release notes.

Block Reference for OR Logic

The full list of OR-family blocks shipped in LSC V8.x:

Inputs can be extended in the block properties dialog (max 8 for B001/B002 in current releases). Excess inputs default to logical 0.

Memory, Performance and Cycle Time

Each logical operation consumes a "function block" slot from the LOGO!'s internal block budget. On a 0BA8 BM with firmware FS:04 or later, the budget is 400 blocks; earlier 0BA8 firmware revisions are limited to 200 blocks. OR logic is inexpensive: a single B001 instance is one block, regardless of whether the contacts are wired in series (AND) or parallel (OR) in the conceptual sense - what matters is the count of B001, B002, B012, B013, etc. blocks in the compiled program.

Cycle time on a 0BA8 BM at 400 blocks loaded is approximately 6 ms per scan with all digital I/O and no expansion modules. OR operations execute in microseconds; they are never the bottleneck. The bottleneck is almost always the SD card write rate (when log is enabled) or the Ethernet/IP poll cycle if the BM is communicating with an external HMI such as a KTP400 or a PLC such as an S7-1200.

Verification: Compiling and Simulating OR Logic

Before transferring the program to hardware, perform this checklist:

1. Press F5 (Compile). The output window must show "No syntax errors" and the block count.
2. Open the simulator (Ctrl+F3).
3. Force I1 = 1, I2 = 0. Confirm Q1 = 1.
4. Force I1 = 0, I2 = 1. Confirm Q1 = 1.
5. Force I1 = 0, I2 = 0. Confirm Q1 = 0.
6. Force I1 = 1, I2 = 1. Confirm Q1 = 1 (no exclusive behavior).
7. Transfer to the BM via Ethernet (Tools → Transfer → PC ↔ LOGO!).
8. On the BM, navigate to Program → Stop, then re-enter Run. The BM display should show the live status of I1, I2, Q1.

Parallel Contacts for Current Sharing - Reliability Caveat

The Siemens support response at support entry 21261393 clarifies that paralleling contactor poles is a recognized technique to increase the AC-1 thermal current rating - the steady-state current capability of a contactor in a purely resistive AC load, defined in IEC 60947-4-1 - when the contacts share a single mechanical drive and therefore close and open within microseconds of each other. The Siemens guidance is explicit:

"Parallel connection of contacts can be used to increase the continuous (thermal) current of a contactor. The AC-1 ratings of contactors can be..."

However, for electronic relay outputs on the LOGO! BM (the four relay outputs on 0BA8 Standard, rated 10 A per contact at 240 V AC / 24 V DC resistive), paralleling two relay contacts to double the switching current introduces reliability problems that the support entry does not address. Field experience and vendor application notes converge on the same conclusion:

• Contact resistance drifts independently on each pole. After a few thousand operations, one pole typically carries 60-80% of the load and ages faster.
• If one contact welds closed (the most common end-of-life failure mode for a small signal relay), the second contact still cycles - and will eventually weld itself. The fault is not detectable by the LOGO! diagnostic.
• The lifetime rating of the LOGO! relay output assumes the rated current passes through a single contact. Doubling the current halves the electrical life per pole, and the load-sharing loss means the actual life is shorter still.

The correct way to switch a load that exceeds one LOGO! relay's rating is to use an external contactor sized for the load, driven by a single LOGO! relay output. For DC loads above the LOGO! rating, use a solid-state relay (SSR) or a DC contactor with a free-wheeling diode across the coil.

Choosing LAD or FBD for Your Project

Use this decision matrix when starting a new LOGO! program:

UDF Wrapping for OR Logic

If you need an OR function across multiple programs, wrap it as a User-Defined Function (UDF). In FBD:

1. Build the OR (B001) plus any NOT, edge, or latching logic in a clean FBD page.
2. Select the block group, choose Tools → UDF → Create from Selection.
3. Define input and output connector pins; LSC auto-generates the connector block in the UDF palette.
4. Save as .lma (LOGO! macro archive) for the project library.

In LAD, the equivalent UDF is more constrained: any flag that the UDF needs to read from outside must be routed through an explicit input pin. Status flags that the UDF sets cannot be exposed through connectors in early 0BA8 LSC builds; they have to be replicated as outputs and consumed inside the parent program.

Edge Cases and Field-Proven Caveats

• Mixed-language programs. LOGO! supports LAD and FBD blocks within the same circuit page as of LSC V8.2. Earlier versions (V8.0, V8.1) require the entire program to be one language. If you migrate an older program to a newer LSC, re-check the language mix after the import.
• Power-up behavior. The LOGO! BM starts all flags at 0 unless they are marked as retentive in the block properties (the "retentivity" checkbox in the OR block's dialog). For an OR block used as a simple combinational gate, retentivity has no effect; for an OR block driving an SR (Set-Reset) flip-flop, retentivity controls whether the Q state survives a power cycle.
• Web server visualization. The LOGO! 8 BM includes a built-in web server. Variables used in OR logic can be exposed under Tools → Web Editor, but only the final coil value (e.g. Q1), not the intermediate OR output, can be displayed on a custom web page. Add a virtual flag and assign it to the OR output if you need to monitor the intermediate value remotely.
• Network variables. When the LOGO! is a slave on Modbus TCP (the 0BA8 BM supports this), the OR output can be read as a single bit but the input contacts cannot be written to the BM from a master. Modbus writes to LOGO! inputs are blocked by the firmware.

Frequently Asked Questions