Siemens S5 CPU 115U 943B Stuck in STOP ISTACK Diagnostics

Overview: S5-115U CPU 943B Stop-Mode Failure After Module Swap

The Siemens SIMATIC S5-115U with CPU 943B (order code 6ES5 943-7UB11 or 6ES5 943-7UB21) is a legacy modular PLC still encountered in cement, water, steel, and power-generation plants where 1980s-vintage installations remain in service. A classic field failure is the controller refusing to transition from STOP to RUN after a hot-swap of an analog input card, with the front-panel LEDs reporting QVZ, ZYK, and BASP. The same symptom can also surface following a backplane reseat, a power dip, or a stack-through of the rack connector. This article reconstructs the standard Siemens diagnostic workflow used to bring the controller back to RUN, identify the failing I/O module, and confirm that the user program on the EPROM/EEPROM sub-module is intact.

CPU 943B Hardware Reference

LED Indicator Decode: What BASP, QVZ, and ZYK Actually Mean

The CPU 943B front-panel LEDs are the first line of diagnostics. Their meaning is standardized across the S5-115U family:

In the original incident, after the first module swap the CPU went to RUN and BASP was cleared, which is why outputs operated normally except for the analog reading. After the backplane was disturbed, the controller entered STOP with QVZ + ZYK + BASP lit. The presence of QVZ together with ZYK is the signature of a QVZ-induced cycle overflow: the CPU scanned the I/O, the backplane did not return a ready signal from one slot, the QVZ exception triggered, and the cycle watchdog elapsed before the CPU could re-enter OB1.

Understanding ISTACK and USTACK on CPU 943B

The S5 diagnostic stack is the equivalent of a modern PLC's fault log. Two views are exposed in STEP 5 (S5-DOS / STEP 5 V7.x) under Test > Stack:

• ISTACK (Interrupt Stack) – captures the interrupt/event that caused the CPU to leave cyclic operation. It is the equivalent of a fault register: it shows the OB that was active, the block stack at the time of the stop, the DB/MB/STW (status word) contents, the last SAC (step address counter), and the cause of stop in the STOP-ID field.
• USTACK (User Stack) – records the call environment of the user block in which the interrupt occurred, useful for tracking a programmed fault into a specific FB/FC.

When the operator initiates a RUN transition from STEP 5 via the PC > PLC > Run/Stop menu, the CPU attempts a cold or warm restart, and if it cannot, the programmer forces a transition to the ISTACK view so the engineer can read the cause-of-stop. The STEP 5 default function key to bypass an ISTACK page and reach the next is F7 (continue), and F6 is typically used to scroll.

Cause-of-Stop Codes Relevant to QVZ

The cause-of-stop byte in ISTACK is decoded using the Siemens manual tables. Excerpts that match this fault pattern:

If the ISTACK shows a QVZ stop-ID pointing to a slot that previously housed the suspect analog card, the rack slot, the backplane, the analog card itself, and the address assignment in DB1 / DX0 must all be considered as candidates.

Step-by-Step Recovery Procedure

1. Power down the rack and isolate the 24 V supply and the 120/230 V mains to the PS 951 power supply module.
2. Remove the lithium backup battery from the CPU front compartment if the program resides in EPROM (submodule is read-only and battery does not protect it). With a battery-backed RAM submodule, leave the battery installed until the rack is verified, otherwise RAM and retentive flags will be erased by the upcoming overall reset.
3. Remove every I/O module from the central rack and any expansion racks, leaving only the CPU and the power supply in place.
4. Power up the rack with only the CPU. The CPU should transition to RUN (or at minimum STOP with no QVZ) because the I/O scan will find no missing modules in the configured base address range. If the CPU is still stuck in STOP with BASP, the fault is in the CPU, the backplane, or the power supply, not the I/O.
5. Press the mode selector on the CPU front panel, or issue the Overall Reset command from STEP 5 (PLC > Memory > Overall Reset). Hold the selector for 3 s until the STOP LED blinks. The CPU returns to a factory-clean state with all flags, timers, counters, and process image zeroed.
6. Re-seat the EPROM submodule. If the program was on a 256 Kbit, 512 Kbit, or 1 Mbit EPROM submodule (e.g., 6ES5 375-1LA15), the program is preserved regardless of battery or power state. Verify with STEP 5 PLC > Information > Module Inventory and confirm the block list.
7. Re-insert one I/O module at a time, powering down between insertions. After each insertion, attempt a RUN. The slot that re-introduces the QVZ is the faulty module or its connector.
8. Replace the failing module. In the recorded incident, the root cause was the analog card SSMD39 (a third-party / vendor-specific 6ES5-form-factor analog input card, sometimes referenced as a 6ES5 460 / 470 compatible). After the replacement, the CPU immediately went to RUN with all other functions operating normally.
9. Re-enable outputs by clearing the BASP latch. BASP is reset on the first successful cold/warm restart, or by the user program issuing the appropriate system call. Confirm the digital outputs respond by jogging one card at a time.
10. Document the ISTACK, the slot of the failed module, the order number of the replacement, the battery install date, and the CPU firmware for the maintenance log.

Verification: Confirming EPROM Program Integrity

A common concern after a backplane disturbance is whether the program in the EPROM submodule has been corrupted. EPROM and EEPROM are non-volatile; they do not lose their contents on power-down, battery removal, or backplane disturbance. To verify program integrity after a service event:

1. In STEP 5, select PLC > Information > Module Inventory. The CPU reports the submodule type and size, the occupied block list (OB, FB, FC, PB, SB, DB, DX), and the free memory.
2. Select PLC > Compare > PLC > Disk to compare the program on the PLC against the STEP 5 project archive on the programming device. Any mismatched block is highlighted.
3. Run a checksum pass on each block (File > Blocks > Check) and compare against the printed reference list from the original commissioning documentation.
4. If the module inventory shows no blocks and the firmware is correct, the EPROM submodule may be unseated, damaged, or the module-inventory read may have been blocked by a STOP condition; reseat the submodule, then re-power the CPU before concluding data loss.

Rack, Backplane, and Power Supply Diagnostics

If the CPU still does not enter RUN with all I/O removed, the fault is in the host system:

Analog Input Card Pitfalls on S5-115U

Analog input cards on the S5-115U (e.g., 6ES5 460-7LA13, 6ES5 465-7LA13, 6ES5 470-7LA12, 6ES5 475-7LA12) require correct parameterization in DB1 / DX0 and a hardware-coded measuring-range module on the side of the card. Common failure modes:

• Wrong measuring range module: ±10 V vs. 0 – 10 V vs. 4 – 20 mA selection. The card returns data but the scaled value is wrong, which is read as "the reading is not coming."
• Loose ribbon between card front connector and the front-panel screw terminal block: a partial contact causes QVZ under load.
• Single-channel short to the field cable: a damaged transducer cable or a miswired shield drain can pull the analog supply down, which the card reports as a parameterization error in ISTACK.
• Loss of the +24 V field supply: many analog cards source their transmitter excitation from an external 24 V rail. If that rail is missing, the card reports QVZ during the first read cycle.

SSMD39-class cards are sometimes pin-compatible third-party analog inputs. Verify the input type, channel count, and parameterization against the original datasheet before substituting, and always update the printed circuit list (the PI/PQ assignment sheet stapled inside the cabinet door).

Preventing the Failure Mode: Best Practices for Module Swap

1. Document slot order with a label on each module and a laminated slot map inside the cabinet. Backplane disturbances become harmless when every module returns to its original slot.
2. Power down before swap. Hot-swap is not supported on the S5-115U backplane; the PS 951 cannot guarantee inrush limiting and a partial insertion will latch QVZ and BASP.
3. Inspect the connector for gold-finger oxidation. Wipe with isopropyl alcohol and a lint-free swab; never use an eraser, which leaves residue.
4. Tighten module screws to the specified torque (typically 0.8 Nm). A loose module can drift out of contact under vibration and intermittently QVZ.
5. Replace the lithium battery every 3 – 5 years, even if BATF is dark. A dead battery at the moment of the next power dip will erase RAM retentive data and cause a STOP on the next restart with ISTACK 0x39xx.
6. Keep a current EPROM image on the programming device and a second EPROM in the cabinet spares drawer.
7. Run a planned BASP test annually. From STEP 5, force BASP via the appropriate system call, verify outputs drop, then clear BASP and verify outputs restore. This proves the BASP path is healthy while the plant is in a safe state.

Decision Matrix: Quick Fault Triage

Long-Term Service Strategy for Legacy S5

The S5 platform has been officially discontinued. Many plants are now executing phased migrations to S7-300/400 or TIA Portal-based S7-1500. While a migration plan is being scoped, the following extends the S5-115U service life:

• Maintain a small stock of 6ES5 943-7UBxx CPUs, 6ES5 7xx I/O, and PS 951 supplies. The surplus market still has refurbished units.
• Use the Siemens Industry Online Support portal to download STEP 5 V7.23 programming software and historical manuals.
• Implement a PC-based HMI (WinCC flexible / TIA WinCC) on a modern OS to retire the obsolete OP/COROS operator panels without disturbing the S5 logic.
• When migrating, use a Siemens-approved gateway (e.g., S5 to PROFINET, 6GK1 414-class gateways) for a phased cutover, keeping the S5 as a sub-system for non-critical loops.

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