Siemens S5 F vs M Bit Addressing: Conversion Reference

Overview

The Siemens SIMATIC S5 family (S5-90U, S5-95U, S5-100U, S5-115U, S5-135U, S5-155U) and its STEP 5 programming environment predate the S7 platform that replaced it. When legacy S5 logic is migrated to a STEP 7 / TIA Portal project — or when code is converted from one platform to the other — the technician must respect platform-specific operand naming. The most common authoring pitfall is the marker bit: an S5 programmer working in the English STEP 5 package writes F10.0, while a German STEP 5 user writes the same operand as M10.0. The S5/S7 converter shipped with early STEP 7 transcribes the prefix literally, so a block originally written in English arrives in STEP 7 as F addresses that the S7 editor will not resolve without a manual replace pass.

This reference documents the S5 marker-bit convention, the behaviour of the S5/S7 conversion utility, a one-shot pulse pattern that survives the round-trip, USB-to-serial connectivity for legacy S5 CPUs on a modern laptop, and the install-time constraints of STEP 5 on 32-bit Windows. The worked example below takes a counter/increment FC, converts it from STEP 7 to STEP 5, validates the result in PLCSIM, and corrects a missing edge-detect that the converter dropped.

S5 Marker Bit Addressing: F vs M

In every member of the S5 CPU family the internal flag (marker) area is a single 2048-bit (2 KB) or larger RAM region used for intermediate boolean and word results. The operand prefix that selects this region is locale-dependent:

All four rows point at the same physical memory. STEP 5 is a single-language runtime — only one of these naming conventions is legal per source file. If the file was written on an English package, the S5 programmer's monitor (PG) will reject M; if the file was written on a German package, the PG will reject F. The language is recorded in the S5 program file header and the S5 CPU itself does not care which prefix was used — it sees raw bit addresses.

To determine which language was used, open the source .S5D or printed listing and look at the first page banner — STEP 5 prints the installed language in the header. Modern PG tools such as the STEP 5 / STEP 7 Converter manual (6ES5 998-0MA24) also display the source language during the import dialog.

S Markers (Special Flags)

Some S5 CPUs expose a second flag region, the S-Marker (special flag), which is a small set of bytes reserved for system-internal use: scan time, restart flags, battery fault, etc. S-markers are addressed identically in every language and are not renamed by the converter:

Use S-markers sparingly and only for the function documented in the CPU manual — they are non-retentive on most CPUs and may be overwritten by the operating system during a warm restart.

S5/S7 Converter Behaviour

The S5/S7 converter bundled with STEP 7 V5.x (and accessible from the SIMATIC Manager under Options → S5/S7 Converter) performs a structural translation rather than a semantic one. The relevant translation rules for marker operands are:

• F → M: any F, FY, FW, FD in the S5 source is rewritten with the S7 operand letter M, MB, MW, MD. The address value is preserved.
• M → F: when the target of the conversion is STEP 5, the inverse substitution is performed. S7's M / MB / MW / MD becomes the English STEP 5 F / FY / FW / FD.
• Output is always English STEP 5: even if the input S7 source used German comments, the emitted STEP 5 file is in English syntax (F, I, Q). To work in German, re-open the result in a German-localised STEP 5 and run the language swap.
• No semantic analysis: jump labels, one-shot edges, and accumulator manipulation are passed through verbatim. The converter does not insert missing edge detection; that is the engineer's job.

Because the output language is fixed, a project that has been round-tripped (S7 → S5 → S7) will, on the second S7 import, contain M operands that the converter originally emitted as F and which the S7 editor will not recognise until a project-wide replace F → M is run.

Worked Example: Counter / Increment FC

The function below is a STEP 7 FC that increments a counter in DB11 each time input I 5.2 is detected as a rising edge, latches the prior count into DBW 0 on the falling edge, and clears the counter on a low input combined with marker M10.1. It was authored in STEP 7 and converted to STEP 5 with the S5/S7 converter.

Original STEP 7 Source (S7-300 / S7-400 STL)

FUNCTION FC 1 : VOID
NAME : BERT
BEGIN
NETWORK
      AN   T 120;
      L    S5TIME#1s;
      SD   T 120;
      //;
      A    T 120;
      AN   I 5.2;
      JC   M001;
      JU   M002;
M001: OPN  DB 11;
      L    DBW 2;
      L    1;
      +I;
      T    DBW 2;
M002: NOP 0;
      A    I 5.2;
      AN   M 10.0;
      JC   M003;
      JU   M004;
M003: OPN  DB 11;
      L    DBW 2;
      T    DBW 0;
M004: NOP 0;
      AN   I 5.2;
      AN   M 10.1;
      JC   M005;
      JU   M006;
M005: L    0;
      OPN  DB 11;
      T    DBW 2;
M006: A    I 5.2;
      =    M 10.0;
      =    M 10.1;
END_FUNCTION

Converted STEP 5 Output (English, emitted by S5/S7 converter)

FUNCTION FC 1 : VOID
NAME : BERT
BEGIN
NETWORK
      AN   T 120;
      L    S5T#1S;
      SD   T 120;
      //;
      A    T 120;
      AN   I 5.2;
      JC   M001;
      JU   M002;
M001: OPN  DB 11;
      L    DBW 2;
      L    1;
      +F;
      T    DBW 2;
M002: NOP 0;
      A    I 5.2;
      AN   F 10.0;
      JC   M003;
      JU   M004;
M003: OPN  DB 11;
      L    DBW 2;
      T    DBW 0;
M004: NOP 0;
      AN   I 5.2;
      AN   F 10.1;
      JC   M005;
      JU   M006;
M005: L    0;
      OPN  DB 11;
      T    DBW 2;
M006: A    I 5.2;
      =    F 10.0;
      =    F 10.1;
END_FUNCTION

Note the substitutions: +I → +F (16-bit integer add, the S5 default fixed-point instruction), and M 10.0 / M 10.1 → F 10.0 / F 10.1. The output is structurally valid STEP 5 STL but the one-shot semantics are not preserved — see the next section.

One-Shot Pulse Generation in S5

In the STEP 7 source the markers M 10.0 and M 10.1 are written unconditionally with the instantaneous value of I 5.2 at label M006. Because the conditional jumps JC M003, JC M005 skip the assignment at M006 in subsequent scans, the markers retain their previous value for one PLC cycle. This produces a classic edge detector: the marker is high for exactly one scan when the input changes state.

After conversion, F 10.0 and F 10.1 are simple flag bits — they have the same physical address as the original M bits, so the one-shot logic does survive the round-trip, but the assumption needs to be verified by simulation. The author's PLCSIM test exposed a subtle issue: the converter did not insert a P-edge instruction (FP) or its S5 equivalent, so the markers are latches driven by the input, not true one-shots. The corrected version uses a single helper bit F 10.2 to capture the timer pulse and then the same JC/JU pattern:

Corrected S5 STL (tested in PLCSIM)

      AN   T 120
      L    S5T#1S
      SD   T 120
      =    F 10.2   // 1-second pulse flag
      //;
      A    F 10.2
      AN   I 5.2
      JC   M001
      JU   M002
M001: OPN  DB 11
      L    DBW 2
      L    1
      +F
      T    DBW 2
M002: NOP 0
      A    I 5.2
      AN   F 10.0
      JC   M003
      JU   M004
M003: OPN  DB 11
      L    DBW 2
      T    DBW 0
M004: NOP 0
      AN   I 5.2
      AN   F 10.1
      JC   M005
      JU   M006
M005: L    0
      OPN  DB 11
      T    DBW 2
M006: A    I 5.2
      =    F 10.0
      AN   I 5.2
      =    F 10.1

The change is the addition of AN I 5.2 immediately before the second assignment at M006, so that F 10.1 tracks the inverse of F 10.0. With this single modification, the block now produces a clean edge on every transition of I 5.2.

PLCSIM Validation Procedure

Always validate converted S5 code in SIMATIC S7-PLCSIM before downloading it to a real CPU. The procedure is:

1. Create a STEP 7 V5.x project and add a SIMATIC 300 station with the CPU 315-2 DP (or any 31x series CPU — the FC does not use CPU-specific instructions).
2. Insert the converted FC into the S7 program sources. Open the FC in the STL editor and manually replace every F operand with M; PLCSIM only loads valid S7 syntax.
3. Create a shared DB11 with the structure DBW 0 : INT; DBW 2 : INT;. Set initial values to 0.
4. Place the FC in OB1 (no instance DB required — it is a VOID FC).
5. Download the entire project to PLCSIM, switch the simulator to Run.
6. Force I 5.2 high, observe DBW 2 incrementing at 1 Hz (driven by T 120). Force I 5.2 low; the next rising edge should copy DBW 2 into DBW 0.
7. Force I 5.2 low while M 10.1 is set; DBW 2 should clear to 0.

If any of the expected transitions are missed, the conversion is not behaviourally equivalent and must be reworked before it is downloaded to the S5 CPU.

Connecting an S5 CPU to a Modern Laptop

Most S5 CPUs in service today (S5-95U, S5-115U) expose only an RS-232 (TTY / V.24) programming port on the front panel. Modern laptops no longer ship with a DB-9 or DB-25 connector; a USB-to-serial adapter is required, and not every adapter works.

STEP 5 selects the COM port under File → Online → Interface. If the dropdown is empty, the VCP driver failed to enumerate — verify the COM number in Windows Device Manager and that it is < 10. Some STEP 5 builds (V6.x and V7.x) hard-cap the COM list at COM4 or COM8.

AS-511 Protocol

S5 online communication uses the AS-511 protocol at 9600 baud, 8 data bits, even parity, 1 stop bit. The protocol is proprietary to Siemens and not documented in the public STEP 5 manuals. Practical points:

• Maximum cable length with a true RS-232 level converter is 15 m. Beyond that, insert an AS-511 repeater.
• The S5 CPU must be in Stop or Run — not Reset — for the online session to establish.
• If the PG reports timeout after the S5 cold restart, cycle power to the CPU and re-attempt the online handshake within 10 s.

STEP 5 Installation on Modern Windows

STEP 5 V7.23 is the last released version and is 16-bit / 32-bit hybrid; the installer is compatible with Windows XP and Windows 7 (32-bit only). Installing on Windows 10 or 11 is not officially supported but is feasible with the following constraints:

The installer does not create a desktop shortcut and writes all binaries under C:\STEP5\S5_ST\BIN. If the program group is missing, launch S5W.EXE directly. The full manual — including installation, project handling, and STL/FBD/LAD editors — is available as the STEP 5 / STEP 7 Converter manual (PDF, 6ES5 998-0MA24).

Code Comparison Reference

Best Practices and Field Notes

• After every S7 → S5 round-trip, run a project-wide search-and-replace F → M before re-importing to S7. The converter does not re-apply its own substitution on the return pass.
• Reserve one F/M byte per FC for local one-shots (the example above uses F 10.0 through F 10.2). S5 timers and F bits are not retentive; a power-cycle will reset them.
• Prefer the S5 FP / FN edge instructions for new code; the JC/JU pattern is necessary only when the original S7 source used it.
• Document the language of every STEP 5 source file in the project header. The next maintainer needs to know whether to expect F or M.
• For CPUs without the extended flag range (S5-100U, S5-95U), keep F/M usage below byte 200 to leave headroom for the operating system.
• When converting ladder (LAD) or function-block-diagram (FBD) sources, the converter emits the equivalent STL — review it line by line; the layout is not preserved.

FAQ