Siemens S5 STEP 5 SLW Instruction: Analog Output Scaling

Overview: S5 Analog Output Processing in STEP 5

The Siemens SIMATIC S5 family uses STEP 5 statement list (STL) programming, where analog input and output values are exchanged with the process through peripheral words (PW). A typical three-instruction sequence such as L FW 204, SLW, T PW 164 is one of the most common patterns seen in legacy S5 analog output code, yet the SLW (Shift Left Word) line is frequently a source of confusion.

The shift is not arbitrary scaling noise. It exists because the bit layout of an S5 analog output peripheral word is not identical to the bit layout of a free flag word. The four low-order bits of the output word are reserved, and the 12-bit data value must be positioned in bits 4 through 15 before the word is written to the output module. SLW is the mechanism that performs this repositioning in a single accumulator operation.

This article covers the STEP 5 SLW instruction in detail, the S5 peripheral word bit layout for analog outputs, the engineering-unit scaling math that maps 0-10 V (or 4-20 mA) to the raw count range, and a complete code walkthrough of the L FW / SLW / T PW pattern. It also contrasts the analog output layout with the analog input layout, lists common field pitfalls, and provides a verification procedure you can run on a live S5-115U, S5-135U, or S5-155U system.

STEP 5 SLW (Shift Left Word) Instruction

SLW is a STEP 5 word-level shift instruction that moves every bit in accumulator 1 one or more places to the left. The mnemonic is SLW <n>, where <n> is the number of bit positions to shift. A shift to the left by n bits is mathematically equivalent to multiplication by 2ⁿ.

The rules for the shift are:

1. Each bit in the 16-bit word moves to the next higher bit number (bit 0 → bit 1, bit 1 → bit 2, and so on).
2. The new low-order bit (bit 0) is always filled with 0.
3. The bit that falls off the high end (bit 15) is discarded and lost. There is no status flag reported back to the program in S5 STL, so the programmer must guard against overflow by keeping the value within the safe range.

Binary:           0110 0001 1001 0110   (decimal 24982)
After SLW 1:      1100 0011 0010 1100   (decimal 49964, low bit filled with 0)
After SLW 1 again:1000 0110 0101 1000   (high bit of the first step is discarded)

A single-bit shift doubles the value. The instruction is the binary equivalent of × 2 and is the most efficient way to perform fast power-of-two scaling on an S5 CPU that lacks a hardware multiplier.

S5 Peripheral Word Bit Layout for Analog Outputs

When the CPU writes to a peripheral word that is wired to an analog output module (for example, the IP 240 or IP 241 in a S5-115U/S5-135U/S5-155U rack), the module does not interpret the full 16 bits as data. The first four bits of the lower-order byte are reserved and are not decoded by the DAC. Only bits 4 through 15 carry the 12-bit output value.

Because the data field occupies bits 4-15, a 12-bit value stored right-justified in a flag word (bits 0-11) must be shifted four places to the left so that the LSB lands on bit 4. The shift count of 4 is fixed by the module hardware; it is not a software setting.

Why the Programmer Inserts SLW Before T PW

Consider the value 0x07FF (decimal 2047), which on a bipolar ±10 V S5 module represents exactly +10 V. If this value sits in flag word FW 204 unmodified, the bit pattern is:

FW 204 = 0000 0111 1111 1111

Loading it directly into accumulator 1 and transferring it to PW 164 would write that exact pattern to the output module. The module would interpret bits 0-3 as reserved, but the data bits (4-15) would be 0111 1111 1111, which is 11 bits, not 12. The full-scale output would be wrong by a factor of 2, and the LSB (bit 4) would carry the bit that was originally bit 0. The DAC would drive approximately +5 V instead of +10 V at a count of 2047.

Inserting SLW 4 in accumulator 1 produces:

FW 204            = 0000 0111 1111 1111   (decimal 2047)
After SLW 4       = 0111 1111 1111 0000   (decimal 32752)
                       ^^^^ data field (bits 4-15)

The 12-bit value is now perfectly aligned to bits 4-15, the four low-order bits are zero, and the module produces the correct analog output. This is the single most important reason the programmer inserted SLW: bit-position alignment, not arithmetic scaling.

Engineering Unit Scaling: Counts to Volts and Milliamps

The shift aligns bits. The actual mapping from a 0-10 V or 4-20 mA engineering value to the raw count range is a separate linear equation and is typically performed in a separate calculation block (FB) or in ladder logic. The most common S5 bipolar module counts are 0-2047 for 0-10 V on a ±10 V module, with 2048 = +10 V and 0 = 0 V (positive half only). For a unipolar 0-10 V module the count range is 0-4095.

For a 0-10 V output on a bipolar module, the linear scaling equation is:

Counts = Engineering_Volts × 204.7

For a 4-20 mA output on a unipolar current module, the standard live-zero conversion is:

Counts = (Engineering_mA - 4) × 256

The scaling calculation produces an integer in the working flag word (here, FW 204). The shift operation then aligns that integer to the peripheral word's data field. Scaling and alignment are two distinct steps; SLW only performs the second one.

Complete Code Walkthrough: L FW 204 / SLW / T PW 164

The literal code listing posted in the question omits the SLW operand. The most common and most physically correct form for a 12-bit analog output module is:

      L   FW 204       // Load scaled count value (0-2047) into ACCU 1
      SLW 4            // Shift left 4 places to align to bits 4-15
      T   PW 164       // Transfer aligned word to analog output channel

Step by step:

1. L FW 204 — reads the 16-bit flag word at address 204 into accumulator 1. Accumulator 2 is loaded with the previous contents of accumulator 1 (standard S5 load behavior). The value should be the linearized integer count, bounded between 0 and 2047 (or the appropriate full-scale count for the configured range).
2. SLW 4 — shifts the 16 bits of accumulator 1 four places to the left. Bit 0 through bit 3 become 0000, and the original bits 0-11 land in bits 4-15. The original bits 12-15 (the upper nibble of the count) are lost; this is acceptable because a 12-bit value never uses those bits. The 16-bit word is now in the exact bit pattern the DAC expects.
3. T PW 164 — writes the shifted word from accumulator 1 to peripheral word 164, which is the process image output area for the analog output channel. The next PLC cycle, the analog output module latches the lower 12 bits and drives the corresponding voltage or current at the field terminals.

Analog Input Bit Layout (For Comparison)

The S5 analog input peripheral word uses a different bit allocation, which is why the SLW operand for inputs is typically 3, not 4.

When the application is reading an analog input, the program typically loads the peripheral word, then evaluates the three status bits in the low byte. The 12-bit data value sits in bits 3-14 (or 3-15, depending on the module family). To isolate the 12-bit value right-justified in a flag word for further arithmetic, the program shifts the loaded word right by 3 (SRW 3) or, equivalently, masks the low byte. The bidirectional relationship is therefore:

• Input: L PW x / SRW 3 / T FW y — right shift to strip the three status bits.
• Output: L FW y / SLW 4 / T PW x — left shift to align to the four reserved low bits.

Common Pitfalls and Bit Misalignment Errors

Cross-Reference: S7 Analog Value Processing Concept

The general principle of analog value processing — acquire, linearize, normalize, and output — is shared across Siemens generations. The conceptual structure documented for the SIMATIC S7-1200 in the TIA Portal manual collection applies equally to S5, even though the specific instructions and bit layouts differ.

In S7, analog input words are 16-bit, the input value of a unipolar voltage channel is normalized to 0-27648 counts, and the conversion is done with the SCALE and UNSCALE instructions. In S5, the count range is narrower (0-2047 for half of a bipolar module, 0-4095 for a unipolar module), and the conversion is implemented manually as a linear calculation followed by a bit shift. The conceptual chain is the same; only the resolution, the normalization range, and the bit position of the data field change.

For reference, the S7-1200 documentation on processing analog values is available in the TIA Portal manual collection (see the official Siemens TIA Portal help portal). The S5 specifics, however, must always be confirmed against the wiring diagram of the installed module.

Field Commissioning and Verification Procedure

After loading the program into the S5 CPU, run this verification sequence before energizing the field wiring:

1. Force FW 204 to KF 0 (constant zero). Verify the field terminal voltage reads 0 V (or 4 mA on a live-zero current output). This confirms SLW does not introduce an offset.
2. Force FW 204 to KF 2047. Verify the field terminal reads +10 V (or 20 mA). This confirms full-scale alignment and that the data field is sitting in bits 4-15.
3. Force FW 204 to KF 1024 (mid-scale). Verify the field terminal reads approximately +5 V (or 12 mA). This confirms linearity through the SLW/transfer path.
4. Force FW 204 to KF 4096 (intentionally out of range). Verify that the output clips at full scale and does not roll over. If the output wraps to 0, the shift is consuming a bit that the DAC does not have, indicating the wrong shift operand for the configured module.
5. Reverse the test on the input side: if the program also reads an analog input, force the input channel with a calibrator at 0 V / 5 V / 10 V and verify that the corresponding flag word updates to 0 / 1024 / 2047 after the SRW 3 mask.

Key Specifications Summary