Siemens S7-1200 Ladder Coils Without Contacts: LAD/FBD Rules

David Krause11 min read
PLC ProgrammingSiemensTIA Portal
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Overview

Programming engineers trained on legacy Step 7 V5.x or third-party controllers often assume that every ( ) coil in a Ladder Diagram (LAD) network must be preceded by at least one normally-open or normally-closed contact, with the contact fed by a Boolean rung condition. The question frequently recurs for the S7-1200, S7-300, and S7-400 families programmed in TIA Portal (Step 7 Basic / Professional): is it legal to drop two or more set/reset coils straight onto the power rail, or to chain three set coils in series with no contact in front of them?

The short answer is yes, with caveats. The PLC execution engine does not interpret the LAD network in the same way a human reader does. The controller compiles the network down to its internal MC7 / AWL/STL-equivalent form and evaluates Boolean state on the basis of Enable EN, ENO, and the actual instruction semantics, not on the visual layout of the rung. As long as the TIA Portal compiler accepts the network, downloads it, and the CPU does not report a consistency error, the program is functionally valid.

There are, however, real situations in which the compiler will reject a coil-less network, mainly when the instruction being placed on the rung expects a Boolean input from the left rail. The remainder of this reference walks through the exact rule, the edge cases, the behavior differences between CPU families, and a step-by-step verification procedure you can run on the bench.

LAD/FBD Display Rules vs. PLC Execution Semantics

Step 7 V5.x and TIA Portal enforce display rules on LAD and FBD networks so that the on-screen view matches IEC 61131-3 graphical conventions. These rules cover:

  • Power-flow direction (left to right, top to bottom)
  • Placement of contacts and coils on the power rail
  • Required Boolean input conditions for boxes, function blocks, and some instructions

These are editor / compiler rules. They are not PLC execution rules. The CPU executes the compiled code; it never reads your graphic. For confirmation, see the Siemens Automation Support entry ID 21952992 - Differences between LAD/FBD and STL/AWL with respect to the rules for graphic display, which clarifies that the CPU cares only about the compiled result, not the visual arrangement of the network.

Concretely, this means that the following networks are functionally equivalent at runtime:

Network Visual layout Compiled result Acceptable?
1 Two set coils in parallel, both fed from the left power rail with no contact Two unconditional SET operations in one cycle Yes, if compiler accepts
2 Three set coils in series, no contacts in front Three unconditional SET operations executed in scan order Yes, if compiler accepts
3 Single set coil, power rail only Unconditional SET in OB1 cycle Yes, if compiler accepts
4 Coil preceded by always-true contact (e.g., %M0.0 latched on) Same compiled result as Network 3 Always accepted
Engineering caution: Networks 1-3 above execute every scan, regardless of program state. Use them only when an unconditional action is intentional, such as initializing a marker, triggering a one-shot via the next instruction, or exercising a debug path. For production control logic, the standard practice is to gate every output behind a defined Boolean condition.

Step-by-Step: Verifying Coils Without Contacts in TIA Portal V11 and Newer

  1. Open or create a project. Launch TIA Portal and create a new project for an S7-1200 (e.g., CPU 1214C DC/DC/DC, 6ES7214-1AG40-0XB0) or S7-1500 target. The behavior is identical for S7-300/S7-400 in Step 7 Professional V11+.
  2. Add a new LAD network in OB1 (Main). Right-click the network number, choose Insert Network, and confirm the language is LAD.
  3. Drag two (S) coils from the bit-logic palette directly onto the right side of the power rail. The first coil should sit on the rail, the second in parallel below it. Do not insert any contact.
  4. Compile the project with Project > Compile > Software (rebuild all blocks). If the status bar reports No errors, the network is valid. If you see a red marker on the network, hover over it for the error code (typical message: "Missing or incorrect input at box" or "No valid input").
  5. Download to the PLC using Online > Download to device. Watch the diagnostics buffer; a clean download will populate OB1 with the two unconditional SET instructions and the CPU will go to RUN.
  6. Go online and monitor the affected tags. Both target bits will be latched to 1 the moment OB1 executes, confirming the coil chain works without a contact.
  7. Repeat for S/R/-(N) and -(P)/-(N) edge coils to confirm that all standard bit-logic output elements compile and execute without a contact prefix.

Instructions That DO Require a Boolean Contact

The compiler is strict whenever the instruction expects a Boolean rung condition, has a fixed left-side input pin, or carries an EN that the LAD/FBD editor treats as a mandatory rung state. The following classes reject a bare power-rail placement:

Instruction family Example Why a contact is required
Timers (TP, TON, TOF, TONR) TON, TP IN pin expects a Boolean edge / level; LAD requires a rung state feeding IN.
Counters (CTU, CTD, CTUD) CTU, CTUD CU and CD are Boolean inputs; cannot be tied to the rail.
Floating-point math ADD_R, MUL_R EN input is part of the box; LAD editor enforces rung state on EN.
Move / conversion MOVE, INT_TO_REAL EN expected; LAD will insert a NO contact automatically if you skip it, but the rung state must exist.
Program control --|CALL|--, JMP Box instructions require a Boolean left input.
Some FBD boxes (S/FP, R/FP edge flags) FP, FN Input is Boolean; tied to the rail forces the compiler to inject a default contact.

If you place one of these instructions on a bare rail, the compiler will either reject the network or auto-insert a --[=1]-- "always true" rung state. In TIA Portal V16-V18, this is rendered as an explicit NO contact on a TRUE constant. In older V11-V13 builds, the editor may show an error code F-0005 ("Invalid input") and refuse to compile until you add a contact or constant.

Behavior Across S7-1200, S7-300, and S7-400

CPU family Typical TIA Portal version Two set coils on rail (no contact) Three set coils in series (no contact) Box instruction on rail
S7-1200 (CPU 1211C / 1212C / 1214C / 1215C / 1217C) V11 - V19 Accepted Accepted Rejected or auto-inserted contact
S7-300 (CPU 312 - CPU 319) V11 - V16 (Classic last) Accepted Accepted Rejected or auto-inserted contact
S7-400 (CPU 412 - CPU 417) V11 - V16 Accepted Accepted Rejected or auto-inserted contact
S7-1500 (CPU 1511 - CPU 1518) V12+ Accepted Accepted Rejected or auto-inserted contact

The behavior is consistent across the families because the LAD compiler, the FBD compiler, and the underlying MC7 / SCL code generator are the same code base in TIA Portal. Differences show up only when the target firmware is older and a specific instruction has been reclassified between versions. For S7-300/S7-400, you may still see the option of generating STL/AWL from the network; the resulting STL is valid even if it would not round-trip back into a clean LAD display.

Why Old School Training Says "Always Use a Contact"

Pre-2000 PLC curricula and IEC 61131-3 stylists argue that every coil should be gated by an explicit condition for three reasons:

  1. Readability. A future maintainer scanning the rung needs to know under what conditions the output fires. An unconditional coil is a maintenance trap.
  2. Traceability. Audited code (e.g., IEC 61508 SIL 2/3 applications) requires that every output be derivable from a defined input condition. A bare coil makes the safety case harder to write.
  3. Defensive design. If somebody later edits the network and moves the coil after a contact, the new contact's state will gate the output. With a bare coil there is no safety net.

For non-safety, debug, or initialization code, the "always-on contact" idiom is a common compromise. The recommended constant contact is a marker that is unconditionally TRUE, often named "TRUE_1" or "AlwaysOn", set once in startup OB100 and never reset. This gives you a rung condition that the LAD editor accepts universally and that the human reviewer recognizes as intentional.

Verification Checklist

Step Expected outcome What to check if it fails
Compile project in TIA Portal Status bar: "0 errors, 0 warnings" Hover red marker; record error code; refer to Siemens Industry Online Support
Download blocks to CPU No download error; CPU enters RUN Check the protection level and the active project; verify IP / PROFIBUS route
Monitor the latched tags online All target bits show value 1 immediately after first OB1 scan Force the watch table; ensure tags are not overwritten by another OB
Cross-view in STL Right-click the network > "Show in STL" shows the corresponding AWL sequence If TIA Portal cannot generate STL, the network is a non-LAD construct (e.g., a textual SCL block)
Cycle time impact Negligible (single-digit microsecond additions) Use the online & diagnostics view > "Cycle time" tab to confirm

Common Use Cases for Coils Without Contacts

  • First-scan initialization. A bare (S) coil in OB100 (or inside an IF "FirstScan" THEN block in SCL) latches a startup marker.
  • Resetting latches on cold restart. A bare (R) on a known address clears the bit on every OB1 cycle, useful for debug override patterns.
  • Forcing a marker high for HMI visibility. Tying a coil to the rail guarantees the bit is always 1, removing a layer of logic from the HMI tag evaluation.
  • Generating a non-retriggerable trigger. Use the bare (S) in front of a --(P)-- edge detector to get a single positive edge per OB1 cycle (acts as a clock generator at the OB1 rate).

Best Practices and Safety Caveats

  • Reserve bare-rail coils for OB100, OB101, debug blocks, or well-commented initialization networks. Production control logic in OB1 should always carry a defined Boolean condition.
  • When the IEC 61131-3 source must round-trip through LAD and FBD editors without information loss, always provide a contact. Some version-control diff tools and the "go to FBD" view are less lossy with explicit rung conditions.
  • For safety-related projects (F-CPU S7-1200F / S7-1500F), the F-Compiler is far stricter. It will reject unconditional coils in the safety program unless they are inside an approved F-block template.
  • Document every bare-rail coil in the program comments. The default TIA Portal comment field is the most efficient place; include the reason ("Init: enable safety reset") and the change-date / author.
  • When migrating from Step 7 V5.5 to TIA Portal V15+, re-validate any STL networks that round-tripped through LAD. The TIA Portal STL parser is stricter about EN/ENO propagation and may flag legacy unconditional coils.
Functional Safety: Never apply the bare-rail coil pattern inside an F-runtime group, F-FB, or F-DB. The F-Compiler enforces a Boolean input condition on every safety-related output. For S7-1200F / S7-1500F see the SIMATIC Safety - Configuring and Programming manual in Siemens Industry Online Support.

Compiler Error Codes You May Encounter

Error code / message Trigger Remedy
"No valid input" / F-0005 Box instruction placed on rail without a Boolean input Add a NO contact, a constant TRUE, or use the auto-inserted default contact
"Missing connection" Parallel branch not closed or coil not wired Close all branches; verify the rail connection on both sides of the coil
"ENO enable required" EN/ENO box wired without a Boolean EN source Add a NO contact to the EN pin
"Type conflict at box input" Data type mismatch on a box parameter Verify operand types match the instruction signature
"Unable to display network in LAD" Network only exists in STL/SCL form Accept the STL representation or rewrite the network in pure LAD

Related Documentation

For the underlying standard, refer to IEC 61131-3:2013, section 5.4 ("Ladder diagram language elements") and section 6.2 ("Declaration and initialization of program organization units"). The standard defines the graphical layout rules but explicitly defers to the vendor on the semantic interpretation of unconditional coils; Siemens's interpretation is "accept if compiler accepts".

For the S7-1200 system manual, see the S7-1200 Programmable Controller System Manual entry 6ES7298-8FA00-8BP0. For S7-300/400 in TIA Portal, see the S7-300/400 in TIA Portal Programming and Operating Manual. For LAD/FBD vs. STL display rules, see the FAQ ID 21952992 in the Siemens Automation Support knowledge base.

Is it legal to write two set coils in parallel with no contact on an S7-1200 in TIA Portal?

Yes. The TIA Portal compiler accepts two (S) coils wired directly to the power rail. The resulting MC7 code unconditionally executes both SET operations on every OB1 scan, and the CPU will run the program without error if the download completes cleanly.

Why does my TIA Portal network compile in V16 but show an error in V13?

Early TIA Portal builds (V11-V13) were stricter about EN/ENO propagation and the absence of a Boolean rung state on certain box instructions. V14+ introduced auto-insertion of a default contact for box instructions, which is why the same network that fails in V13 may compile in V16. Check the editor's online help for the specific error code and consider upgrading or inserting a manual NO contact.

Can I use a bare-rail coil inside a safety program on an S7-1200F or S7-1500F?

No. The F-Compiler in the SIMATIC Safety package enforces a Boolean input condition on every safety-related output. A coil placed directly on the rail is rejected at compile time. Use a defined safety input tag or a constant TRUE from a validated safety source.

How do I show the equivalent STL for a network with two bare-rail coils?

Right-click the LAD network and choose Go to > STL representation (or View > STL depending on the TIA Portal version). The compiler will generate the AWL sequence SET followed by S <tag1>, S <tag2>, which you can confirm by stepping through the STL online with the watch table.

Does an unconditional bare-rail coil consume more cycle time than a contact-gated coil?

No. The compiled MC7 instruction sequence is essentially identical; the gate contact compiles to a single Boolean load that the CPU executes in tens of nanoseconds. Cycle-time differences are immeasurable on any modern S7-1200/1500 CPU. The choice between a bare coil and a gated coil is a readability and safety concern, not a performance concern.

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