Siemens S7-200 High Speed Counter (HSC) Setup, Limits

1. Overview of the S7-200 High Speed Counter

The S7-200 CPU family (CPU 221, 222, 224, 224XP, 226) integrates dedicated High-Speed Counters (HSCs) implemented in hardware so that pulse trains arriving on the CPU's digital inputs can be counted independently of the OB1 scan time. Six HSC channels are defined in the platform: HSC0 through HSC5, although the number of physical input terminals wired to each channel depends on the specific CPU and on the selected counting mode. Maximum input frequencies documented by Siemens range from 20 kHz on most CPUs up to 200 kHz on the CPU 224XP for the dedicated high-speed inputs I0.0/I0.1, with the remainder of the inputs limited to 30 kHz single-phase. The HSC mechanism is described in detail in the S7-200 SMART System Manual (the S7-200 SMART inherits the same HSC architecture with extended frequency limits) and in the legacy Siemens Industry Online Support knowledge base for the classic S7-200.

The HSC is started and parameterised by two instructions: HDEF (High-Speed Counter DEFinition) to assign the mode and initial I/O assignments, and HSC to load the new control byte and begin operation. In most engineering environments the HSC Wizard in STEP 7 Micro/WIN automatically generates a subroutine called HSC_CTRL that wraps the HDEF and HSC calls and exposes a defined interface (Mode, CV, PV, New_RV, New_CV, etc.).

2. Counter Value Data Type and Numeric Range

The current value of every S7-200 HSC is stored internally as a 32-bit signed double integer (DINT). The legal range is therefore:

• Minimum: -2,147,483,648 (0x80000000)
• Maximum: +2,147,483,647 (0x7FFFFFFF)

The original poster's question concerning values such as "-2312313 to 212313" is a typographical representation of this DINT limit. The displayed decimal values are simply user-defined subset limits chosen for a particular application (for example, "run between 0 and 100"); the hardware itself can count across the entire signed 32-bit range. Any logic that loads a new reference value (NEW_RV) or writes the current value (CV) must respect this DINT range, otherwise the HSC will saturate or the HSC instruction will reject the value.

3. HSC Modes, Inputs, and I/O Assignment

The HDEF instruction selects one of 12 modes (0-11) for each HSC. The table below summarises the modes available on the S7-200 family. Inputs prefixed with a bullet (•) are dedicated to the HSC and cannot be used as ordinary I/O while the mode is active.

4. HSC_CTRL Subroutine Interface

The HSC Wizard generates a subroutine with a fixed local variable table. The pins exposed in the standard HSC_CTRL block are:

The NEW_RV input is the most commonly misunderstood parameter. It is the value that will be loaded into CV (or used as a reset target) at a defined event such as CV = PV, external reset, or HSC-direction change. It is stored in the special memory area of the HSC and is transferred to the counter only when the configured event occurs, not immediately upon writing the variable. This is what makes the field report's example (running between 0 and 100) feasible: PV=100 is configured, an interrupt is attached to CV=PV, and inside the interrupt the user program calls HSC_CTRL with New_CV = 0 to reload the counter at the next scan of the HSC instruction.

5. Control Byte Definition

When the HSC instruction executes, it reads a control byte in the special memory (SMB) area to determine which options are active. The standard layout is:

Setting bit 5 forces the HSC to take the value at the New_CV input on the next clock pulse. Setting bit 6 forces the HSC to update the reference value from New_RV. The HSC Wizard exposes these flags as direct local variables so the user does not have to manipulate the SMB byte manually.

6. Hardware Interrupts Attached to HSCs

The S7-200 supports hardware interrupts triggered by HSC events. Each HSC channel can be configured to fire an interrupt on:

1. CV = PV (current value equals preset value)
2. Direction change (counting up vs. counting down)
3. External reset event

The interrupt service routine is a standard subroutine attached to the relevant interrupt event in STEP 7 Micro/WIN. The recommended pattern is:

1. Set PV to the desired trigger value (e.g., 100) in the HSC_CTRL block.
2. Attach the CV=PV interrupt to a dedicated OB (e.g., INT_0).
3. Inside INT_0, call HSC_CTRL again with New_CV := 0 and a one-shot write to bit 5 to force the counter back to 0.
4. On the next scan, HSC resumes counting from 0 up to 100, creating a modulo-100 counter that never overflows the DINT range.

7. Example: Modulo-100 Counter with Reload on CV=PV

The following STL excerpt illustrates the pattern discussed in the source thread. Comments mark the wizard-generated variables.

// Main OB1 - count from 0 to 100 indefinitely
NETWORK 1
LD       SM0.1                // First scan flag
CALL     HSC_INIT, 0, 4, 0, 100, 0, 0, HSC_Done
//                       |  |  |   |    |  |
//                       |  |  |   |    |  +-- New_RV = 0 (initial)
//                       |  |  |   |    +----- New_CV = 0 (initial)
//                       |  |  +---+---------- PV = 100 (preset)
//                       |  +---------------- Mode 4 (single-phase, reset)
//                       +------------------- HSC0

NETWORK 2
LD       Always_On
ATCH     INT_HSC0, 12         // Attach CV=PV interrupt (event 12 for HSC0) to INT_HSC0
ENI                          // Enable global interrupt

// INT_HSC0 - reload counter to 0 on CV=PV interrupt
NETWORK 1
LD       SM0.0                // Always true inside interrupt
SI       HSC0_CV_W, 1         // Set bit 5 of control byte (write CV)
SI       HSC0_EN, 1           // Set bit 7 (HSC enable retained)
CALL     HSC_CTRL, 0, 4, 0, 100, 0, 0, HSC_Done
// New_CV = 0 forces CV back to 0 on next HSC tick

For a CPU 224XP running at 200 kHz, the above counter wraps every 100 counts, so the application logic that reads HSC0_CV always receives a value in the 0-99 window. The original DINT range is never approached.

8. Frequency Limits per CPU

9. Comparison with CLICK PLC and ControlLogix HSCs

While the source is focused on the S7-200, it is useful to compare the HSC architectures on the other platforms covered in the additional research.

For the CLICK family, the HSC function block is configured through the CLICK programming software's dedicated HSC setup screen; the CLICK HSC encoder tutorial walks through wiring and parameterisation. For the 1756-HSC module, refer to the 1756-HSC user manual for register definitions, scaling, and the CIP messaging interface.

10. Troubleshooting Matrix

11. Field Commissioning Checklist

1. Confirm encoder supply voltage (typically 24 VDC, sometimes 5 VDC) matches CPU input threshold.
2. Wire the encoder's A channel (and B, Z where used) to the dedicated HSC input pair defined in the mode table.
3. Set the HSC filter group in the CPU system block to the lowest acceptable filter for the chosen frequency.
4. Call HDEF once on first scan (SM0.1). Subsequent calls on the same HSC will return a non-fatal error.
5. Program the first-scan preload of New_CV if the application must start from a known value.
6. Attach the CV=PV interrupt and call HSC inside the interrupt to reload the counter if a modulo range is required.
7. Monitor HSC0_CV (or the relevant channel) using a status chart and apply a slow pulse train to validate counting direction.
8. Increase the pulse rate to confirm the HSC does not drop counts at the operating frequency.

12. Frequently Asked Questions