Siemens S7 Non-Standard Pulse: Clock Memory, TP, OB35

Overview: Why "Non-Standard" S7 Pulse Generation

The classic Siemens S7 timer block (S_PULSE, S_PEXT, S_ODT, S_OFFDT) is designed to time an output, not to produce a fixed-cadence, one-scan event. When a program needs a heartbeat pulse such as "set bit X for exactly one OB1 cycle, every 1000 ms," none of the S5 timer blocks deliver it directly. The output of S_PEXT, for example, stays high for the entire programmed duration regardless of input behavior, which makes it unsuitable for sub-scan pulse generation without additional edge logic.

This reference documents five field-proven techniques for generating a non-standard, fixed-period, single-scan pulse on the Siemens S7-300, S7-400, S7-1200, and S7-1500 families. Each method is evaluated against scan-time jitter, CPU load, programming clarity, and portability across the STEP 7 / TIA Portal toolchain.

Target applications include:

• Heartbeat bit for sequence-step advancement
• Triggering of integrator FB inputs on a fixed cadence
• Watchdog refresh from HMI to PLC at 1 Hz
• Incrementing cycle counters used for recipe scheduling
• Time-stamping event logs from a known period source

Prerequisites and Platform Mapping

Before selecting a method, confirm the CPU family and firmware. The timer instruction set differs substantially between the legacy S5-style blocks (used in S7-300/S7-400 with STEP 7 V5.x) and the IEC 61131-3 timers used in S7-1200/S7-1500 with TIA Portal.

Verify the CPU clock memory byte is enabled. On the S7-300/400, open HW Config, double-click the CPU, select Cycle/Clock Memory, tick Clock memory, and assign a memory byte (commonly MB0 or MB10). The default frequency map assigns bit 7 = 0.5 Hz, bit 6 = 1 Hz, bit 5 = 2 Hz, and continues doubling down to bit 0 = 0.5 Hz at a 10 s period. For a 1-second pulse use Mx.6. Refer to the Siemens Industry Online Support CPU manual for the exact bit-to-frequency mapping of your specific CPU order number.

Method 1: CPU Clock Memory + Edge Detection

The simplest and most deterministic method on the S7-300/400. The clock memory bit toggles in the CPU system clock independent of OB1 scan time, providing a hardware-derived 1 Hz signal. Combine it with a positive edge instruction to convert the level into a one-scan pulse.

Ladder (FBD/ST) on S7-300/400:

Network 1 - 1-second heartbeat pulse
  M0.6      Pulse_1s      M10.0
--| |-------| P |---------( )--
  |         edge |
  M0.6          |
--| |-----------/

The P (positive edge) contact detects the rising edge of M0.6 and closes its contact for exactly one OB1 scan. The closing of M10.0 increments a counter or triggers downstream FBs.

ST equivalent (SCL) on S7-1200/1500:

// In OB1 main cycle
IF "Clock_1Hz" THEN
    IF NOT "Edge_Memory" THEN
        "Heartbeat_1s" := TRUE;   // pulse for this scan
    END_IF;
    "Edge_Memory" := TRUE;
ELSE
    "Edge_Memory" := FALSE;
    "Heartbeat_1s" := FALSE;
END_IF;

On S7-1200/1500, edge detection is built into the IEC timer instructions. Use TP with PT = 1 ms on the clock bit, or use the R_TRIG instance directly. The standard IEC form is preferred over manual edge memory because it is glitch-free.

Field caveat: the pulse width is exactly one OB1 scan. If the consumer FB is called in a different OB or with conditional call logic, the pulse may be missed. Place the pulse network in OB1, first network, unconditional, to guarantee observation.

Method 2: S5 Extended Pulse Timer (S_PEXT)

The S_PEXT block (German: Verlängerter Impuls) holds its output high for the programmed duration regardless of how briefly the input was triggered. It is the only S5 timer whose semantic is closer to a one-shot, but the output still lasts the full programmed PT, not one scan. To get a one-scan pulse, cascade S_PEXT with a negative edge on its output to retrigger the timer itself.

Network 1 - Extended pulse self-cycling
   M100.0         T1
--| |-----------|S_PEXT|
   S5T#1S        |    Q  |
                |    M100.0
                +--------+
Network 2 - Reset T1 on falling edge of Q
   M100.0        T1
--|/|-----------|R      |

Behavior:

1. First scan: M100.0 is FALSE, T1 is idle, no Q output.
2. At scan N, M100.0 goes TRUE momentarily; T1 latches and starts the 1 s PT.
3. At scan N + 1, the user logic resets T1 via the negative edge of M100.0 in Network 2.
4. T1's Q output M100.0 stays high for the full PT; the negative edge detector in Network 2 only fires when M100.0 transitions back to 0.

Method 3: Self-Resetting S5 On-Delay Timer (S_ODT)

This is the most field-validated pattern for S7-300/400 when a hardware clock memory bit is not available or not desired. The timer's own output is used to disable its own input, producing a clean one-cycle low-going edge on the next scan after PT elapses.

Network 1 - Self-cycling 1 s pulse
  M3.1          T5
--|/|---------| S_ODT  |
  S5T#1S      |       Q|
              |   M3.1|
              +-------+

Scan-by-scan trace:

1. Scan 0: M3.1 = 0, T5 input = 1 (inverted contact), T5 starts timing.
2. Scan N at 1 s: T5's Q output rises, M3.1 = 1, T5 input = 0, T5 holds the output but stops timing.
3. Scan N + 1: Logic re-evaluates, T5 input is now 0, T5 resets on the next cycle, M3.1 = 0, T5 input = 1, T5 starts timing again.

This produces a square wave on M3.1 with period ≈ 1 s + 1 scan. The duty cycle is nearly 50 percent, which makes it unsuitable for a one-scan pulse per se, but you can derive a one-scan pulse from the rising edge of M3.1 using a positive edge contact.

Improvement for a true one-scan pulse:

Network 1 - M3.1 Q drives edge
  M3.1          M3.2
--| |----|P|-----( )--   // M3.2 = 1 scan pulse at 1 Hz

Method 4: OB35 Cycle Interrupt

OB35 is a hardware-interrupt OB that runs at a configurable interval independent of OB1. On S7-300 the default is 100 ms, configurable down to 1 ms. On S7-400 multiple cycle OBs (OB30-OB38) are available with different default periods. By placing the pulse-set logic in OB35 with PT = 1000 ms, you get a deterministic, scan-independent trigger.

Configuration (HW Config, CPU 315-2DP):

1. Open HW Config, double-click the CPU.
2. Select Cycle Interrupts.
3. Set OB35 priority (default 12) and period (e.g. 1000 ms).
4. Click OK and download HW Config.

Code in OB35 (first network):

  "Heartbeat_1s"     "OB35_Tick"
----( S )------------( )--

// In OB1, last network:
  "OB35_Tick"        "Heartbeat_1s"
----( R )---------------( )--

The set occurs in OB35, the reset occurs in OB1 on the next scan. The result is a pulse that is high for one OB1 cycle, fired at exactly 1 Hz by OB35. If OB1 scan time exceeds the OB35 period, a pulse can be missed — a critical constraint for slow scans (typ. >500 ms).

Advantages: independent of OB1 jitter; can be prioritized above the main cycle; supports time-of-day OB10-OB17 alternatives for absolute-time triggers.

Disadvantages: requires OB1-OB35 cross-reference; obscure to debug without cross-reference view; missed pulses on slow scans.

Method 5: TP (Generate Pulse) Instruction (S7-1200/1500)

The TP IEC 61131-3 timer is a hardware-style pulse generator. Its semantics differ from S_PULSE: the output Q is set for exactly the programmed PT duration starting from the rising edge of IN, independent of how long IN stays high. Use it as the cleanest one-shot primitive on S7-1200/1500. Reference: TP: Generate pulse (S7-1200, S7-1500) - TIA Portal V20 documentation.

SCL signature:

"MyTP"(    IN  := "Clock_1Hz",
           PT  := T#1s,
           Q   => "Pulse_1s",
           ET  => "TP_Elapsed");

Behavior:

• On rising edge of IN: Q = 1 for PT, ET counts up from 0 to PT.
• Q remains 1 even if IN drops to 0 during the PT.
• A second rising edge of IN during the active PT is ignored; Q continues until PT elapses.

To get a one-scan pulse from a 1-second PT, you still need a downstream R_TRIG or P contact on the rising edge of Q, because Q stays high for the full 1 s. The TP gives you a level-clean, retrigger-immune gate; edge detection gives you the one-scan event.

Field caveat on S7-1500 with firmware <V2.0: certain TP instances in optimized data blocks could reset the ET output on edge re-trigger, causing downstream integrators to lose count. Upgrade to firmware V2.5 or later, or use the IEC_TIMER system data type which is firmware-agnostic.

Scan Time and Jitter Considerations

Every method above interacts with the OB1 scan time differently. The table below summarizes the jitter envelope for a target 1000 ms period on a CPU 315-2DP with a typical 20 ms scan.

Diagnostic tip: if the consumer FB occasionally misses a pulse, place a sticky bit in the FB that is set when the input pulse is observed and reset only after the FB has acted on it. A second occurrence within the same scan is then caught in the consumer rather than lost in the producer. This is the same defensive pattern as a hardware interrupt flag in a microcontroller ISR.

For applications that need sub-millisecond accuracy (e.g. motion profiles), the above methods are inadequate. Use the S7-1500 MC_Power/MC_MoveVelocity clock or the S7-1200 CTRL_HSC high-speed counter instead — they have hardware-derived timing independent of OB1.

Edge vs Level: Why Positive Edge Detection Fails Without Discipline

A common pitfall is using a positive edge contact directly on a slow-changing signal (e.g. an analog comparator or a debounced switch). The P (FBD) or R_TRIG (SCL) instruction samples the input, compares to the previous scan, and outputs 1 only on a 0→1 transition. This is correct, but the user must ensure that the input is sampled only once per scan — duplicating the instruction in multiple networks will cause inconsistent edge behavior, because each instance maintains its own edge memory.

OSR (One-Shot Rising) for S7-300/400 in LAD:

Network 1
   M0.6         M10.0         M10.1
--| |----|OSR|--------------|
   (bit_in)    (bit_out)     |
   M0.6                       |
--|/|---------|R|            |

The OSR block on the S7-300 is in the Bit Logic folder of the LAD/FBD library. It outputs the input level only on the scan that the input transitions from 0 to 1, and holds the output high for that single scan. A separate reset network on the negative edge of M0.6 prevents re-triggering within the same high period.

Method Comparison Matrix

Verification and Commissioning Procedure

After deploying any of the methods above, verify the pulse with a VAT (Variable Table) or watch table:

1. Open STEP 7 or TIA Portal, open a watch table containing the pulse bit and a counter word (e.g. MW100).
2. Add a line that increments the counter on the pulse, e.g. MW100 = MW100 + 1 as an ST snippet bound to the pulse bit, or use the built-in modify-with-trigger.
3. Go online, enable monitoring, force the pulse bit off, then enable the clock memory or OB35.
4. Observe the pulse bit toggle at 1 Hz with a one-scan high time in the timing diagram.
5. Verify the counter increments by exactly 60 each minute, with no skipped or double counts.

Trace tool on S7-1500: configure a trace recording of the pulse bit and a free-running time stamp for 30 s, then check the period histogram. Mean period should be 1000.0 ms ±2 ms; standard deviation below 1 ms indicates the clock memory or TP path is healthy.

FAQ