Siemens STEP 7 --(P)-- and --(N)-- Edge Contacts: Migration from S7-200 MicroWIN to STEP 7 and TIA Portal

1. Overview

The --|P|-- (positive edge) and --|N|-- (negative edge) contacts familiar to engineers using the SIMATIC S7-200 MicroWIN programming software do not exist as named, parameterless instructions in classic STEP 7 (SIMATIC Manager) or in TIA Portal. Their functional equivalent is the --(P)-- and --(N)-- coil-style instruction found in the Bit Logic folder of both editors, and the P_TRIG / N_TRIG function blocks (or the legacy POS / NEG / FP / FN instructions) used in FBD and SCL/ST.

The single most important difference between MicroWIN and STEP 7 / TIA Portal edge detection is the requirement for an explicit edge memory bit. In S7-200 MicroWIN, the |P| and |N| instructions automatically use a hidden internal flag. STEP 7 and TIA Portal force the programmer to allocate a unique boolean tag (M, DB, I, Q, or instance) to each edge instruction, and the editor refuses to compile the block until that assignment is made.

This reference covers the LAD, FBD, and SCL/ST forms of the instruction, the edge memory bit rules, the migration procedure from S7-200 to S7-300/400/1200/1500, and the most common pitfalls (shared tags, scan-order dependencies, retained vs non-retained memory).

2. Edge Detection Fundamentals

An edge is a state transition of a boolean signal during one PLC scan. Two transitions are meaningful in discrete control:

• Positive edge (rising edge): signal changes from 0 (FALSE) to 1 (TRUE). Often abbreviated as P or RE.
• Negative edge (falling edge): signal changes from 1 (TRUE) to 0 (FALSE). Often abbreviated as N or FE.

The output of an edge instruction is TRUE for exactly one OB1 scan cycle when the transition is detected, and FALSE in all subsequent scans until the input transitions again. This one-shot behavior is the foundation of event counters, latching logic, debounce-free transition recognition, and pulse generation.

Mathematically, a positive edge on input IN with edge memory M is computed as:

The edge memory bit therefore stores the previous state of the input. Two independent edge instructions must never share the same edge memory bit, because each write would corrupt the other's stored previous state and suppress or duplicate edges.

3. P and N Contacts in S7-200 MicroWIN (Legacy Reference)

On the S7-200 platform, the MicroWIN instruction set exposes two contacts in the Bit Logic toolbar:

• --|P|-- — positive (rising) edge contact. Closed for one scan when the upstream logic transitions from FALSE to TRUE.
• --|N|-- — negative (falling) edge contact. Closed for one scan when the upstream logic transitions from TRUE to FALSE.

A typical MicroWIN network evaluates a rising edge on the boolean M10.1 and, on detection, sets output Q0.0:

M10.1                 Q0.0
----| |-------|P|--------( )---

MicroWIN automatically allocated an internal edge memory bit in the system area (V memory region) and managed the previous-state storage internally. The programmer was not required to specify or even know which bit was used. This convenience is the single biggest source of confusion when the same logic is re-implemented on S7-300/400 or S7-1200/1500.

The S7-200 product line reached end of life in 2017. New applications should be implemented on S7-1200/1500 with TIA Portal, and existing S7-200 logic should be migrated using the conversion paths described in section 9.

4. --(P)-- and --(N)-- in Classic STEP 7 (SIMATIC Manager, S7-300/400)

Classic STEP 7 (versions V5.x) and the SIMATIC Manager provide the following edge instructions in the Bit Logic folder of the program editor:

The LAD --(P)-- and --(N)-- appear as coil-type elements at the right end of a rung, although they are functionally contacts in the sense that they make a one-shot TRUE pulse available to downstream logic. The symbol matches the --( )-- assignment coil, with a P or N letter inside the parentheses.

To reproduce the MicroWIN example above, the engineer must:

1. Allocate a free boolean tag for the edge memory, e.g. M10.2.
2. Insert the --(P)-- instruction from the Bit Logic folder and assign M10.2 above the coil symbol.
3. Wire the upstream RLO (the result of the M10.1 contact) into the --(P)-- input.
4. Use the --(P)-- output as the energizing input to the assignment coil that drives Q0.0.

The equivalent classic STEP 7 network looks like this:

      M10.2
M10.1     Q0.0
----| |-----------(P)----------( )----

The M10.2 tag above the --(P)-- coil is the edge memory bit. It is the parameter that MicroWIN hides from the user; in classic STEP 7 it must be made explicit. The same tag is reserved exclusively for this one edge instruction.

5. --(P)-- and --(N)-- in TIA Portal (S7-1200 / S7-1500)

TIA Portal exposes the same instructions with the same naming convention as classic STEP 7, with the addition of a dedicated Edge Memory Bit (M_BIT) input parameter that is more clearly surfaced in the tooltip and F1 help. The official TIA Portal help for the S7-1200 instruction set describes the positive edge contact as follows:

"Scan operand for positive signal edge. LAD: The state of this contact is TRUE when a positive transition (OFF-to-ON) is detected on the assigned IN bit, otherwise it is FALSE. The edge memory bit stores the previous state of the IN bit."

The TIA Portal implementation, however, is more forgiving: the editor can auto-generate an edge memory bit from the project symbol table when one is not explicitly assigned, marking it with the prefix <Edge>. This convenience feature is enabled by default in TIA Portal V15.1 and later, and it stores the bit in an automatically-managed instance DB or in the PLC tags area. Auto-generated edge bits can be identified in the cross-reference by the editor-assigned name.

For a fully explicit and self-documenting implementation, the engineer should still create a dedicated edge memory tag in the PLC tags table and assign it manually:

// PLC tags
Tag          Type    Address
Edge_M10_1   Bool    M10.2   // edge memory for M10.1 rising edge

The TIA Portal LAD network for the migrated logic is identical in appearance to the classic STEP 7 version:

      Edge_M10_1
M10.1          Q0.0
----| |--------------(P)--------( )----

For S7-1500, the same --(P)-- instruction is implemented in optimized block access, meaning the edge memory bit must be located in a tag that the compiler can resolve to a single bit of a byte/word/dword. TIA Portal V18 and later automatically marks edge memory tags as non-optimized-compatible; if the block uses optimized access, the tag must be a standalone Bool.

6. Edge Memory Bit Assignment Rules and Best Practices

Whether the project uses classic STEP 7 or TIA Portal, the following rules apply to the edge memory bit (M_BIT):

1. Uniqueness. No two --(P)-- or --(N)-- instructions may share the same M_BIT. Sharing causes one edge to overwrite the other's stored previous state.
2. Single-bit width. M_BIT must resolve to a single boolean. Assigning a byte (e.g. MB10) is not allowed; the tag must be of type Bool at a bit address (e.g. M10.2).
3. Non-retained or retained? Use a non-retained bit (default for M area) so that a power-cycle resets the edge history. Retained bits carry the last state across restarts, which can produce a spurious edge on the first scan after a warm restart if the input is already TRUE.
4. No re-use of the same bit as a normal flag. The same tag must not be SET, RESET, or assigned in another network. The compiler does not enforce this, but doing so corrupts the stored previous state and causes missed or duplicate edges.
5. Single scan-cycle exposure. The pulse is true for exactly one OB1 cycle. Any downstream logic that requires the pulse for longer than one cycle must latch it explicitly.
6. Order of evaluation. In LAD/FBD, the --(P)-- must be reached in the same scan in which the input transitions. Re-ordering rungs can change which edge is detected first when two edges share a common trigger network.

A common naming convention used in industrial code reviews is to name the edge memory bit with a _EM_ suffix or to bind it inside a dedicated edge data block (DB). For multi-instance patterns, an instance DB of a function block containing the edge instruction is preferred to ensure uniqueness through the compiler-generated DB number.

7. LAD, FBD, and SCL/ST Equivalents

The following table shows the three representations of a rising edge on a boolean input bStart that sets a latch bLamp. The edge memory bit is bEdgeStart. All three forms compile to identical machine code on S7-1200/1500.

      bEdgeStart
bStart      bLamp
----| |-----------(P)-------(S)---

bStart -----|P_TRIG  |--- bLamp
          |CLK Q|--(S)
          |M_BIT |
          |bEdgeS|

IF bStart AND NOT bEdgeStartPrev THEN
    bLamp := TRUE;
END_IF;
bEdgeStartPrev := bStart;

For S7-300/400 STL, the rising edge of bStart with edge memory bEdgeStart is written as:

// STL (S7-300/400)
A     bStart        // AND input
FP    bEdgeStart    // positive edge on M_BIT
S     bLamp         // set latch if edge detected

For the falling edge, the LAD contact --(N)-- is the mirror image. In STL the equivalent is FN:

// STL (S7-300/400) - falling edge
A     bStop
FN    bEdgeStop
R     bLamp         // reset latch on falling edge of bStop

8. P_TRIG and N_TRIG Function Block Alternative

In TIA Portal V13 and later, the P_TRIG and N_TRIG blocks (and their older aliases R_TRIG and F_TRIG) are available in the Bit Logic → Edge Detection folder. They are functionally identical to --(P)-- / --(N)-- but expose a multi-instance interface, which is the recommended pattern in S7-1500 programs that follow the PLC Open style:

• P_TRIG (positive / rising edge detector): inputs CLK and M_BIT; output Q.
• N_TRIG (negative / falling edge detector): inputs CLK and M_BIT; output Q.

When the block is called from a function block (FB) using multi-instance capability, the edge memory bit is stored in the instance DB, guaranteeing uniqueness by construction. This is the preferred pattern for engineers migrating S7-200 code that contained dozens of |P| and |N| instructions, because the instance DB approach eliminates the bookkeeping required to allocate unique M bits.

A minimal SCL example of a multi-instance P_TRIG inside an FB:

FUNCTION_BLOCK FB_Conveyor
VAR
    iRun : BOOL;                  // run input
    iRunEdge : P_TRIG;            // multi-instance edge detector
    bRunLatch : BOOL;             // latched run bit
END_VAR

IF iRunEdge.CLK := iRun; iRunEdge() THEN
    bRunLatch := TRUE;
END_IF;

Note that when the multi-instance P_TRIG is used, the M_BIT parameter is stored in the instance DB and is therefore allocated by the compiler, eliminating the unique-tag bookkeeping error class entirely.

9. Step-by-Step Migration Procedure from S7-200 to STEP 7 / TIA Portal

The following procedure applies to engineers porting S7-200 MicroWIN programs (using |P| / |N|) to a modern controller. The procedure is the same whether the target is an S7-300/400 with classic STEP 7 or an S7-1200/1500 with TIA Portal.

9.1 Prerequisites

• The S7-200 source program in MicroWIN (.mwp or .mwt format) or exported as a STEP 7 source file.
• A target controller firmware version that supports the required instructions: S7-300/400 firmware ≥ V2.0 for STL FP / FN (universal), S7-1200 firmware ≥ V4.0 for full TIA Portal edge support, S7-1500 firmware ≥ V1.0 (all instructions available out of the box).
• A TIA Portal installation matching the target controller family, version ≥ V16 SP1 for S7-1200/1500 (V18 or later is recommended for current projects).
• An empty edge memory data block (DB) or a reserved M area, e.g. MB100..MB199, dedicated exclusively to edge bits.

9.2 Migration Procedure

1. Inventory the edge instructions. Open the S7-200 program and count every |P| and |N| contact. Record the upstream RLO tag and the downstream consumer tag for each. The micro-grained inventory is the input to the next step.
2. Allocate unique edge memory bits. For each edge, assign a unique boolean tag in the reserved M or DB area. Use a naming convention such as Edge_<source>_P / Edge_<source>_N.
3. Insert the new instructions. In the target editor, locate Bit Logic → --(P)-- and --(N)--. Drag the instruction into the rung, or in LAD double-click the rung terminus and type --|P|-- (TIA Portal auto-completes to --(P)--).
4. Assign the edge memory bit. Click the M_BIT placeholder above the coil symbol and type the allocated tag, or pick it from the PLC tag table dropdown.
5. Wire the network. Connect the upstream contact (the original | | instruction that was left of |P|) to the input of the --(P)-- and connect the output to the original downstream consumer (typically a coil, set, or reset).
6. Reserve an instance DB pattern where practical. For S7-1500, encapsulate each edge in a multi-instance P_TRIG or N_TRIG inside an FB. The compiler will then allocate edge memory automatically and uniqueness is enforced by the data block structure.
7. Re-validate the network. Use the Compile command. STEP 7 and TIA Portal both raise a compile error if the edge memory bit is missing or assigned to a non-boolean tag.

9.3 Verification on the Target Controller

1. Download the project to the target PLC and put it in RUN.
2. Force the upstream contact to 0 using the watch table / monitor and modify window.
3. Toggle the contact to 1 and observe the edge bit and the downstream output. The edge bit should remain 0 for at least one full scan after the rising edge is processed.
4. Use a trace recording in TIA Portal (S7-1500 only) or the VAT (variable status table) to confirm that the --(P)-- output is TRUE for exactly one OB1 cycle.
5. Repeat the test for a falling edge: confirm that --(N)-- output is TRUE for one cycle on the 1→0 transition only.

10. Common Pitfalls and Diagnostics

The following matrix lists the most frequent defects introduced by migration from S7-200 MicroWIN, the symptom, and the corrective action.

11. Advanced Use Cases

11.1 Generating a Fixed-Width Pulse

The single-cycle pulse of --(P)-- is too short for some HMI or fieldbus handshake sequences. To generate a fixed-width pulse, the standard pattern is to combine --(P)-- with a self-resetting timer:

// LAD pattern (TIA Portal)
       bEdge_M  TON "PulseTimer"
--| |---------------(P)----(IN)----
                            PT = T#200ms

When --|P|-- fires, it sets the IN of the on-delay timer for one cycle. The timer then runs to its preset (200 ms in this example) and resets, producing a clean 200 ms pulse regardless of the input transition.

11.2 Debounced Edge from a Mechanical Input

Mechanical contacts produce contact bounce that can register as multiple edges within a few milliseconds. The --(P)-- instruction alone will fire multiple times during the bounce window. The recommended mitigation is to pass the input through an IEC timer configured for the bounce time (typically 5–20 ms) before feeding it to the edge instruction:

// Debounce with on-delay timer
iRawSwitch -> TON bDebounced, PT = T#10ms
bDebounced -> --(P)-- with bEdgeDebounce memory bit

11.3 Counting Events

The standard pattern for counting events uses the CTU IEC counter and the --(P)-- instruction as the count trigger:

// Counter increment on rising edge of bPartDetected
bPartDetected ----(P)---- CTU iCounter, PV := 1000

12. References and Official Documentation

• TIA Portal Help: Positive and Negative Edge Instructions (S7-1200)
• SIMATIC S7-1200 Programmable Controller System Manual
• SIMATIC TIA Portal V18 Programming and Operating Manual
• SIMATIC S7-300 CPU 31xC and CPU 31x: Installation and Operating Manual
• SIMATIC S7-1200 Programmable Controller: System Manual (current edition)
• SIMATIC S7-1500 Automation System: Function Manual