SIMATIC STEP 7 Signal Generator: Square, Sine, Triangle Waves

David Krause20 min read
PLC ProgrammingS7-300Siemens
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1. Overview: Signal Generation on a SIMATIC PLC

A signal generator in a controller context is a program that produces a periodic waveform on a digital or analog output with controllable frequency, duty cycle, and amplitude. On a SIMATIC platform the achievable signal quality is bounded by two physical limits: the OB1 cycle time of the CPU (typically 10 ms to 150 ms on S7-300/S7-400) and the resolution of the output module. Square waves up to several kHz are practical on a digital output; sine waves are realistically limited to 5-10 Hz when synthesized in the user program and routed to a 12-bit analog output; clean triangle waves are practical up to a few hundred Hz. Above those limits the controller either needs a dedicated frequency, counter, or PWM module (FM 350, FM 450, ET 200S PWM) or an external function generator triggered from the PLC over Profinet or Profibus.

According to the general definition, a signal generator is a device that produces electrical signals with controlled amplitude, frequency, and waveshape. The same three parameters map directly onto the SIMATIC implementation: amplitude is set by scaling the integer output value (0-27648 for a 0-10 V SM 332), frequency is set by the phase increment per scan or by a clock memory bit, and waveshape is selected by the chosen function (square, sine, triangle, ramp).

This reference covers four waveform families on SIMATIC S7-300 / S7-400 with STEP 7 V5.x and the SIMATIC Manager:

  • Square wave from clock memory bits (0.125 Hz to 10 Hz, no user code required)
  • Square wave from a TON/TOF pair (any frequency below OB1 cycle / 2)
  • Sine wave from a SIN() call or a 360-step lookup table scaled to SM 332
  • Triangle wave from an up/down counter scaled to SM 332

PWM on S7-200 and S7-1200 is summarized for comparison, since those platforms have native PWM instructions that reach tens to hundreds of kHz without cycle-time constraints.

If you need a clean analog waveform above 100 Hz with low THD, the correct architecture is an external DDS or XR2206-class analog front end, with the PLC supplying only the trigger and setpoint. Trying to push the OB1 cycle below 1 ms is fragile on S7-300/400 and gains only an octave of useful bandwidth.

2. Platform Selection: STEP 7 Classic vs. TIA Portal

STEP 7 V5.5 / V5.6 (the "classic" environment with the SIMATIC Manager) is the historical toolchain for S7-300, S7-400, and WinAC. TIA Portal (V13 to V19 today) is the unified successor for S7-1200, S7-1500, ET 200, and most S7-300/400 work as well. Both can host a signal-generator FB. The differences that matter for waveform generation are summarized below.

Feature STEP 7 V5.5 (Classic) TIA Portal (V13-V19)
Programming languages STL, LAD, FBD, SCL, GRAPH, HiGraph LAD, FBD, SCL, GRAPH, STL (limited)
Default target S7-300, S7-400, WinAC S7-1200, S7-1500, S7-300/400
Clock memory bits HW Config > CPU > Cycle/Clock Memory tab CPU Properties > System and Clock Memory
Native PWM instruction No (requires FM or DO + filter) Yes (CTRL_PWM, SFB for S7-1500)
PWM max frequency (native DO) Not applicable 100 kHz on S7-1200 signal board, 4 kHz on standard DQ
SIN/COS function blocks STL inline; SCL intrinsic SCL intrinsic (SIN, COS, TAN, ASIN, ACOS, ATAN)
Analog output resolution SM 332: 12-bit, ±10 V / 0-10 V / 4-20 mA SM 332, AQ modules: 12-16 bit
OB1 minimum cycle 1-150 ms typical 1 ms typical (firmware cycle)

For pure waveform experimentation, TIA Portal on an S7-1200 / S7-1500 is faster to iterate. For brownfield S7-300 stations, STEP 7 V5.5 with SCL is the most productive path because the OB1 cycle is predictable and the SIN function in SCL compiles to a few IEC 61131 floating-point instructions.

3. Hardware Prerequisite: Output Modules

You will need at least one of the following:

  • Digital output module (SM 322, DO 32x24V/0.5A) for square wave / PWM.
  • Analog output module (SM 332, AO 8x12Bit, 6ES7332-5HF00-0AB0) for sine / triangle / arbitrary waveform.
  • Frequency / counter module (FM 350-1, FM 350-2) for high-frequency square or PWM up to 500 kHz.

Output range selection on SM 332 channels:

Output Range Raw Integer Per LSB Notes
0 - 10 V 0 to 27648 361.69 µV Unipolar, most common
±10 V -27648 to +27648 361.69 µV Bipolar, requires channel configured for ±10 V
1 - 5 V 0 to 27648 144.79 µV Live-zero, alarms on wire break
0 - 20 mA 0 to 27648 723.4 nA Unipolar current
4 - 20 mA 0 to 27648 578.7 nA Live-zero, standard industrial
4 - 20 mA HART 0 to 27648 (over range 0-29312) 578.7 nA Used with HART multiplexers
Standard SM 332 channels are configured per channel in HW Config under "Outputs" > "Output Range". Selecting ±10 V requires the bipolar variant (6ES7332-5HB01-0AB0 or 6ES7332-5HD01-0AB0) and removes the live-zero error detection.

4. Square Wave Generation with Clock Memory Bits

The fastest path to a square wave on any S7-300/400 is the clock memory byte. Each bit toggles at a fixed period driven by the CPU. You enable the byte in HW Config and route a single bit directly to a digital output.

4.1 Enable the Clock Memory Byte

  1. Open SIMATIC Manager and load HW Config for the S7-300 station.
  2. Double-click the CPU (for example 6ES7315-2EH14-0AB0, CPU 315-2 PN/DP).
  3. Open the "Cycle/Clock Memory" tab.
  4. Tick "Clock memory", set the "Memory byte" address (for example MB 200), and confirm.
  5. Save, compile, and download the hardware configuration.

4.2 Default Clock Memory Periods

Bit (with MB 200) Period Frequency Typical Use
M 200.0 0.1 s 10.0 Hz Heartbeat / "running" lamp
M 200.1 0.2 s 5.0 Hz Slow blink
M 200.2 0.4 s 2.5 Hz Slow indicator
M 200.3 0.5 s 2.0 Hz Strobe warning
M 200.4 1.0 s 1.0 Hz 1-second tick
M 200.5 2.0 s 0.5 Hz Watchdog kick
M 200.6 4.0 s 0.25 Hz Slow timer
M 200.7 8.0 s 0.125 Hz Hourly tick (approx.)

4.3 Wire the Bit to a Digital Output

Place a single contact-coil network in OB1, FC1, or a dedicated FB:

// LAD / FBD equivalent:
NETWORK 1: Square wave 5 Hz on Q 124.0
  M 200.1       Q 124.0
--| |--------------( )--

The output Q 124.0 will toggle every 0.2 s (50% duty, 5 Hz). This requires zero user code beyond a single contact and is fully deterministic because the clock memory bit is updated in the system clock interrupt, not in OB1.

The clock memory byte is driven by the CPU's internal timer and is not affected by OB1 cycle jitter. However, the digital output transition itself is synchronized to the OB1 read/write boundary, so on slow CPUs you may see a one-cycle delay between the bit toggle and the physical output update.

5. Square Wave Generation with TON/TOF Timers

For a variable-frequency square wave that you control from the user program (HMI setpoint, recipe, or function block parameter), use an on-delay timer feeding a flip-flop:

// SCL implementation (STEP 7 V5.5 SCL)
FUNCTION_BLOCK FB1 "SquareWaveTimer"
VAR_INPUT
    iPeriod    : TIME;     // full period, e.g. T#1s for 1 Hz
    bEnable    : BOOL;
END_VAR
VAR_OUTPUT
    qOutput    : BOOL;
END_VAR
VAR
    sToggle    : BOOL;
    sT1        : TON;      // half-period on timer
    sT2        : TOF;      // half-period off timer (optional, debounce)
END_VAR
BEGIN
    IF bEnable THEN
        sT1(IN := NOT sT1.Q, PT := iPeriod / 2);
        IF sT1.Q THEN
            sToggle := NOT sToggle;
            sT1(IN := FALSE);  // re-trigger
        END_IF;
        qOutput := sToggle;
    ELSE
        qOutput := FALSE;
        sToggle := FALSE;
        sT1(IN := FALSE);
    END_IF;
END_FUNCTION_BLOCK

Minimum selectable period is two OB1 cycles (one high, one low). With a 100 ms OB1 the floor is 200 ms (5 Hz); with a 10 ms OB1 the floor is 20 ms (50 Hz). For frequencies above the OB1 ceiling, use FM 350-1 counter module or the CTRL_PWM instruction on S7-1200/S7-1500.

OB1 cycle Min period Max frequency Use case
150 ms (default S7-314) 300 ms 3.33 Hz Process / status blink
100 ms (S7-315) 200 ms 5.0 Hz Indicator, alarm beacon
50 ms (cycle-observer loaded) 100 ms 10.0 Hz Audio tone (low quality)
10 ms (S7-317 minimum) 20 ms 50.0 Hz Mains half-cycle simulation
1 ms (S7-1516 in TIA) 2 ms 500 Hz Audible alarm, low-speed PWM

6. Higher-Frequency PWM on S7-200 and S7-1200

The S7-200 and S7-1200 families have PWM generators that operate independently of OB1 and are driven by hardware, so the user program only sets frequency and duty cycle. This is the correct choice when you need a clean square/PWM above the OB1 ceiling.

6.1 S7-200 PWM

The S7-200 PWM output (PTO/PWM generator on Q0.0 or Q0.1) supports:

  • Frequency range: 0 to 20 kHz in PTO mode, 0 to 100 kHz in PWM mode (CPU 224 XP, 226)
  • Duty cycle: 0 to 100% in 1 µs steps (PWM), 50% fixed (PTO)
  • Independent of OB1 - the waveform is hardware-timed

6.2 S7-1200 PWM

The CTRL_PWM instruction in TIA Portal on S7-1200/S7-1500 supports:

  • Standard DQ: 0.1 Hz to 4 kHz (100 kHz on S7-1500 high-speed DQ)
  • Signal board DQ: up to 100 kHz
  • Duty cycle: 0 to 100% in 0.1% increments
  • Hardware-timed, OB1-independent
For S7-300/400 there is no native CTRL_PWM equivalent on the standard DQ. PWM at high frequency on S7-300 requires an FM 350-1 / FM 450 counter/frequency module, or an external PWM amplifier driven from a single digital output through an RC low-pass filter (for low-frequency analog reconstruction only).

7. Sine Wave Mathematics and the SIN Instruction

For a sine wave you need to evaluate v(t) = A · sin(2π · f · t) + offset once per scan and write the result to the analog output. STEP 7 SCL provides a built-in SIN() function that takes a REAL argument in radians and returns a REAL in [-1, +1].

7.1 Phase Increment Calculation

To advance the phase by a constant amount per scan:

phase_increment [rad/scan] = 2 * PI * target_frequency [Hz] * OB1_cycle [s]

Example: target 2 Hz, OB1 100 ms
  phase_increment = 2 * 3.14159265 * 2 * 0.1 = 1.2566 rad/scan
  (full 2*PI revolution = 6.2832 rad, so the loop period is 5 scans = 0.5 s = 2 Hz)

7.2 Nyquist Limit

Maximum synthesizable frequency is bounded by the Shannon-Nyquist theorem: f_max < 1 / (2 · t_scan). For an OB1 cycle of 100 ms the upper bound is 5 Hz, so a 2 Hz sine is comfortably synthesized. Pushing past 5 Hz produces visible stairstep distortion in the output.

OB1 cycle Nyquist f_max Recommended max sine Stair-step amplitude
150 ms 3.33 Hz 2.0 Hz 0.59 V at 10 V peak (6%)
100 ms 5.00 Hz 3.0 Hz 0.38 V at 10 V peak (3.8%)
50 ms 10.0 Hz 6.0 Hz 0.19 V at 10 V peak (1.9%)
20 ms 25.0 Hz 15.0 Hz 0.076 V at 10 V peak (0.76%)
10 ms 50.0 Hz 30.0 Hz 0.038 V at 10 V peak (0.38%)

The stair-step amplitude column shows the worst-case voltage error between the held analog output and the ideal sine curve. For 1% THD, keep the target frequency at or below the "Recommended max sine" column.

8. Sine Wave with Lookup Table and Analog Output

For maximum smoothness and minimum CPU load, pre-compute the sine values once and step through a 360-entry DB. The lookup avoids a transcendental function call per scan, so the cycle-time budget is dominated by the analog-output write.

8.1 Generate the Lookup DB

  1. Create DB 200 "Sine360" with 360 REAL values.
  2. Initialize the table once on startup (in OB100) with a FOR loop, or import from a CSV/Excel file via the S7 source editor.
// SCL initialization block (OB100, restart)
FOR i := 0 TO 359 DO
    Sine360[i] := SIN( INT_TO_REAL(i) * 3.14159265 / 180.0 );
END_FOR;

8.2 Step Through the Table in OB1

FUNCTION_BLOCK FB10 "SineWaveLUT"
VAR_INPUT
    iAmplitude : REAL;    // peak voltage (e.g. 5.0 for 0..10V swing)
    iOffset    : REAL;    // DC bias (e.g. 5.0 to centre on 5V)
    iFrequency : REAL;    // 0.01 .. 5.0 Hz typical
    bEnable    : BOOL;
END_VAR
VAR_OUTPUT
    qOutputRaw : WORD;    // raw value 0..27648
    qOutputV   : REAL;    // computed voltage
END_VAR
VAR
    sIndex     : INT;     // 0..359 step index
    sIncrement  : REAL;   // step per scan
    sScanTime  : REAL;   // OB1 cycle in seconds
    sSample    : REAL;
END_VAR
BEGIN
    IF bEnable THEN
        sScanTime  := 0.1;        // match actual OB1 cycle
        sIncrement := iFrequency * 360.0 * sScanTime;
        sSample    := Sine360[sIndex];
        qOutputV   := iOffset + sSample * iAmplitude;
        qOutputRaw := REAL_TO_WORD( LIMIT(0.0, qOutputV / 10.0, 1.0) * 27648.0 );
        sIndex     := sIndex + REAL_TO_INT(sIncrement);
        WHILE sIndex >= 360 DO sIndex := sIndex - 360; END_WHILE;
        WHILE sIndex <   0 DO sIndex := sIndex + 360; END_WHILE;
    ELSE
        qOutputRaw := 0;
        qOutputV   := 0.0;
    END_IF;
END_FUNCTION_BLOCK

8.3 Scaling Formulas

To convert a desired voltage in V to the raw SM 332 integer (0-10 V range):

raw_word = LIMIT(0, ROUND( (V_out / 10.0) * 27648.0 ), 27648)

To recover voltage from a raw integer:
V_out = (raw_word / 27648.0) * 10.0

For ±10 V bipolar range, allow raw values from -27648 to +27648 and divide by 2764.8 to get volts. If you are limited to the 0-10 V unipolar range, you must bias the sine with a DC offset equal to the peak amplitude (offset = amplitude) so the output never goes negative. For a 0-10 V output with peak 5 V, use offset = 5 V and amplitude = 5 V to swing between 0 V and 10 V.

The integer divider on S7-300/400 is 16-bit signed. WORD arithmetic wraps at 65535; INT arithmetic wraps at 32767/-32768. If your scaled value exceeds 32767 you must use DINT (REAL_TO_DINT) and then move the low word to the output process image, otherwise you get wraparound. Using SCL with REAL_TO_WORD does the conversion correctly, but the result is an unsigned 16-bit word that you then S7-move to PQW.

9. Triangle Wave Generation

A triangle wave ramps linearly from 0 to peak over half a period, then from peak back to 0 over the next half. The implementation is an up/down counter whose current value is scaled to the analog output.

FUNCTION_BLOCK FB20 "TriangleWave"
VAR_INPUT
    iAmplitude : REAL;     // peak voltage, e.g. 10.0 for 0..10V
    iFrequency : REAL;     // 0.01 .. 20.0 Hz
    bEnable    : BOOL;
END_VAR
VAR_OUTPUT
    qOutputRaw : WORD;
    qOutputV   : REAL;
END_VAR
VAR
    sUp        : BOOL;     // direction flag
    sPosition  : REAL;     // 0.0 .. 1.0 normalized
    sStep      : REAL;     // step per scan
    sScanTime  : REAL;
END_VAR
BEGIN
    IF bEnable THEN
        sScanTime := 0.1;
        sStep     := 2.0 * iFrequency * sScanTime;   // full sweep = 2*freq*scan
        IF sUp THEN
            sPosition := sPosition + sStep;
            IF sPosition >= 1.0 THEN
                sPosition := 1.0;
                sUp       := FALSE;
            END_IF;
        ELSE
            sPosition := sPosition - sStep;
            IF sPosition <= 0.0 THEN
                sPosition := 0.0;
                sUp       := TRUE;
            END_IF;
        END_IF;
        qOutputV   := sPosition * iAmplitude;
        qOutputRaw := REAL_TO_WORD( (qOutputV / 10.0) * 27648.0 );
    ELSE
        qOutputRaw := 0;
        qOutputV   := 0.0;
        sPosition  := 0.0;
        sUp        := TRUE;
    END_IF;
END_FUNCTION_BLOCK

A triangle wave has higher harmonic content than a sine but lower than a square. At 5 Hz with a 100 ms OB1 the reconstruction error is well under 1%. The frequency limit is approximately twice the sine limit (around 10-20 Hz) because the slope is gentle near the peak and aggressive at the zero crossings; the analog output holds a constant value during a scan, so the slope is well represented in the linear region.

10. Complete Example: Multi-Waveform FB in SCL

The following function block combines square, sine, and triangle generation in one place so the HMI can select the waveform with a single selector switch.

FUNCTION_BLOCK FB50 "SignalGenerator"
VAR_INPUT
    iMode        : INT;      // 0=off, 1=square, 2=sine, 3=triangle
    iFrequency   : REAL;     // Hz
    iAmplitude   : REAL;     // peak V (0..5 if iOffset=5 on 0..10V output)
    iOffset      : REAL;     // V DC bias
    bEnable      : BOOL;
END_VAR
VAR_OUTPUT
    qOutputRaw   : WORD;
    qOutputV     : REAL;
END_VAR
VAR
    sSquare      : FB1;      // from section 5
    sSine        : FB10;     // from section 8
    sTriangle    : FB20;     // from section 9
END_VAR
BEGIN
    CASE iMode OF
        0:                                        // off
            qOutputRaw := 0;
            qOutputV   := 0.0;
        1:                                        // square
            sSquare(iPeriod := REAL_TO_TIME(1.0 / iFrequency * 1000.0),
                    bEnable := bEnable);
            qOutputV   := SEL(BOOL_TO_REAL(sSquare.qOutput), iOffset, iOffset + iAmplitude);
            qOutputRaw := REAL_TO_WORD( (qOutputV / 10.0) * 27648.0 );
        2:                                        // sine
            sSine(iAmplitude := iAmplitude,
                  iOffset    := iOffset,
                  iFrequency := iFrequency,
                  bEnable    := bEnable);
            qOutputRaw := sSine.qOutputRaw;
            qOutputV   := sSine.qOutputV;
        3:                                        // triangle
            sTriangle(iAmplitude := iAmplitude,
                      iFrequency := iFrequency,
                      bEnable    := bEnable);
            qOutputRaw := sTriangle.qOutputRaw;
            qOutputV   := sTriangle.qOutputV;
    END_CASE;
END_FUNCTION_BLOCK

Place an instance DB (DB50 "SignalGen") of FB50, call FB50 from OB1 with iMode bound to an HMI tag, and write qOutputRaw to the process image of the SM 332 output channel (for example PQW 288 for channel 0 of module 4 in slot 4).

11. Frequency, Period, and Amplitude Calculations

Reference formulas for sanity-checking any waveform configuration in the field:

Period from frequency:        T = 1 / f
Frequency from period:        f = 1 / T
Phase increment per scan:     dphi = 2 * PI * f * t_scan
Nyquist ceiling:              f_max = 1 / (2 * t_scan)
Half-period delay:            t_high = t_low = T / 2 (square, 50% duty)
Duty cycle:                   D = t_high / T  (0..1)
PWM average:                  V_avg = D * V_supply

SM 332 voltage to raw:        raw = ROUND( (V / V_range) * 27648 )
SM 332 raw to voltage:        V   = (raw / 27648) * V_range
SM 332 current 4-20 mA:       I   = 4 + (raw / 27648) * 16 [mA]

For a 4-20 mA loop driving a remote indicator the equivalent raw range is 0-27648 mapping to 4-20 mA. 0 mA (0 raw) is the underrange fault; 21.0 mA or above (raw 29030) is the overrange fault. Standard function generators do not deliver current; the SM 332 voltage output can drive a 4-20 mA loop only if the channel is reconfigured to current mode in HW Config.

12. Verification, Diagnostics, and Troubleshooting

Verification sequence after downloading the FB and starting the generator:

  1. Connect an oscilloscope or multimeter to the SM 332 output terminals (e.g. channel 0: pin 3 = +V, pin 4 = ground/return for voltage, or pin 1 = +I, pin 2 = -I for current).
  2. Open the FB in STEP 7 online, force bEnable = TRUE and iMode = 2 (sine).
  3. Set iAmplitude = 5.0, iOffset = 5.0, iFrequency = 1.0.
  4. Observe: 0-10 V sine, 1 Hz, 50% duty on both halves of the cycle. Period 1000 ms, peak-to-peak 10 V (0 V to 10 V at the terminals).
  5. Change iFrequency to 3.0. Verify the period shortens to ~333 ms and the shape is still smooth (no flat-top distortion).
  6. Set iMode = 3 (triangle). Verify the slope changes sign at 0 V and 10 V.
  7. Set iMode = 1 (square). Verify the duty cycle is 50% and the amplitude swings full-scale.

Troubleshooting Matrix

Symptom Likely Cause Diagnostic Remedy
Output is stuck at 0 V FB not called from OB1, or bEnable = FALSE, or PQW wrong address Online > Monitor DB50, check bEnable and qOutputRaw Call FB50 from OB1; verify PQW matches HW Config slot
Output is stuck at 10 V (rail) Wrong channel range (configured 0-10 V but driven as ±10 V); overflow on raw value Check SM 332 diagnostics LEDs; monitor PQW Reset channel to correct range; clamp output to 0-10 V before write
Output saturates at 0 V and 10 V (square wave instead of sine) REAL_TO_INT overflow because of unscaled values; sine evaluation broken Monitor raw integer; check for > 27648 or sign extension Use REAL_TO_DINT then WORD cast, or use the SCL LIMIT() function
Square wave on Q is missing or inverted Clock memory byte not enabled, or wrong address Monitor M 200.1 online; check HW Config > Cycle/Clock Memory Enable clock memory, save/compile/download HW Config
Sine looks stair-stepped OB1 cycle too long for target frequency Measure OB1 actual cycle in CPU online diagnostics Lower target frequency, or reduce OB1 cycle time, or switch to FM 354 servo module for high-speed output
Frequency is half the expected Phase increment added twice (once in FB1, once in OB1) Grep for additional SIN calls; online variable trace Move phase accumulator to a static VAR with retention; call only from OB1
Output drifts / wanders Float accumulated error in sIndex or sPhase Check sIndex range, sPhase wrap Wrap sIndex to [0, 360) and sPhase to [0, 2*PI) on every scan
Output is noisy (mV-level spikes) Common-mode pickup on shielded output cable; no shield ground Scope with differential probe; check shield Use shielded twisted pair, ground shield at one end only at the SM 332 terminal block
CPU goes STOP with SF (system fault) Analog module diagnostic interrupt unhandled; channel configured but module missing CPU diagnostic buffer Install OB82 (diagnostic interrupt) or match HW Config to physical rack
Frequency setpoint from HMI has no effect iFrequency is INT (rounded to 0 or 1 Hz) Tag list in HMI tags Change HMI tag type to REAL, update PLC tag type to REAL

Performance Notes

  • SIN() in SCL on S7-315 takes roughly 12-25 µs per call. A 360-step lookup avoids this cost and runs in under 5 µs per scan.
  • Writing PQW from OB1 takes one bus cycle (typically 1-3 ms across the backplane). For deterministic output, write the value in a cyclic interrupt OB (OB35-OB38) at a fixed period (for example 100 ms), not from OB1.
  • If multiple analog channels are driven, write them in order of slot number to minimize backplane turnaround.

13. Frequently Asked Questions

What is the maximum sine-wave frequency a SIMATIC S7-300 can synthesize in the user program?

Approximately 3-5 Hz with the default 100-150 ms OB1 cycle, bounded by the Nyquist limit (f < 1 / (2 · t_scan)). A 100 ms OB1 supports up to 5 Hz; a 10 ms OB1 supports up to 50 Hz. For higher frequencies, use a high-speed analog module (SM 332 with 0.1 ms settling), the FM 354 position module with sine output, or an external DDS generator.

How do I enable the clock memory byte in STEP 7 V5.5?

Open HW Config, double-click the CPU, open the "Cycle/Clock Memory" tab, tick "Clock memory", set the memory byte address (for example MB 200), save, compile, and download the hardware configuration. Bit 0 (M200.0) toggles at 10 Hz, bit 7 (M200.7) at 0.125 Hz, with 50% duty cycle.

Can I generate a clean ±10 V sine on a standard 0-10 V SM 332 output?

No. A standard SM 332 6ES7332-5HF00-0AB0 outputs 0-10 V unipolar. To get a bipolar sine you must (a) use the bipolar ±10 V variant of the module and configure the channel for ±10 V, or (b) bias the sine with a 5 V DC offset on a 0-10 V channel and accept the 0-10 V unipolar swing (offset = 5 V, amplitude = 5 V).

How do I scale a voltage in V to the raw SM 332 integer (0-10 V)?

raw_word = ROUND((V_out / 10.0) * 27648), clamped to 0..27648. For 4-20 mA the equivalent formula is raw_word = ROUND(((I_out - 4) / 16) * 27648), clamped to 0..27648. In SCL use REAL_TO_WORD with a LIMIT() guard to prevent wraparound.

Why is my sine wave outputting a square wave on the scope?

Integer overflow on the raw value (REAL_TO_INT producing values outside 0..27648, wrapping to -32768), or the FB is not being called every scan and the PQW holds the last value. Monitor qOutputRaw online, clamp to 0..27648, and confirm OB1 is actually calling the FB by toggling a debug bit in the FB and watching it in VAT.

What is the difference between clock memory bits and PWM on S7-1200?

Clock memory bits are fixed-frequency, 50%-duty toggles driven by the CPU system clock, and are independent of OB1. They cannot be changed in frequency or duty cycle. PWM on S7-1200 (CTRL_PWM) is hardware-timed, independent of OB1, and supports variable frequency (0.1 Hz to 4 kHz on standard DQ, 100 kHz on signal board) and variable duty cycle (0-100%) set from the user program.

Can I use the SIN instruction in STL on S7-300?

Yes. In STL, the SIN function operates on accumulator 1 (REAL) and replaces the value with the sine in radians. Example: L "AngleRad"; SIN; T "SineResult"; with both tags declared as REAL. SCL is generally preferred for readability, but STL is the lower-latency path if every microsecond counts.

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