SM 1231 0-12 Vdc Voltage Divider: Resistor Sizing and Wiring

Problem Overview

Many legacy analog sensors, transducers, and laboratory instruments output a 0-12 Vdc signal rather than the industry-standard 0-10 Vdc range accepted by Siemens SIMATIC SM 1231 analog input modules. Without external signal conditioning, the over-range input will be clipped at the module's full-scale value (typically 10 V), and any voltage between 10 V and 12 V will appear simply as +32767 in the S7-1200 process image, completely obscuring the true value of the signal.

This article documents a field-proven method of scaling a 0-12 Vdc source into the 0-10 Vdc input window of an SM 1231 channel using an external resistor-based voltage divider, including:

• Voltage divider theory and the 12:10 (6:5) ratio derivation
• Resistor value, tolerance, and power-rating selection
• Loading-error analysis against the SM 1231 input impedance
• Differential wiring practice for S7-1200 SM 1231 channels
• TIA Portal hardware configuration of the analog input
• Software scaling to recover the original 0-12 Vdc engineering units
• Five more accurate alternatives to a discrete resistor divider
• Step-by-step verification, calibration procedure, and troubleshooting matrix

If your source is in fact bipolar or has a different range, see the Alternative Signal Conditioning Methods section first.

SM 1231 Module and Voltage Range Reference

The SM 1231 family is the analog input slice module (SM) used in the SIMATIC S7-1200 PLC system. The catalog variants in service today include:

Voltage ranges are configured per-channel in TIA Portal. For a 0-12 Vdc source that must occupy the full measurement range, configure the channel as Voltage ±10 V bipolar if the polarity never reverses and you have scaling headroom to recover the missing half-scale, OR configure to a true unipolar 0-10 V range if your catalog variant supports it. Note that some 13-bit SM 1231 variants expose only bipolar ±10 V, not unipolar 0-10 V — review the channel configuration tree in TIA Portal for the exact option set of your catalog number before proceeding.

For official specifications, refer to: SM 1231 Analog Input Module Technical Specifications on Siemens Industry Online Support.

Key SM 1231 Analog Input Characteristics

Prerequisites

Before wiring a 0-12 Vdc source into an SM 1231 input, confirm the following:

1. CPU and module compatibility. The SM 1231 must be installed on the signal-module bus of an S7-1200 CPU (any current catalog CPU 1211C, 1212C, 1214C, 1215C, or 1217C). The system supports up to 8 SMs per CPU. Consult the S7-1200 system manual for the per-CPU maximum slot budget.
2. TIA Portal project accessible. A configured project with the SM 1231 in the device view and the analog-input range set to "Voltage 0-10 V" or "Voltage ±10 V" depending on your catalog variant.
3. Source characterization. Confirm: (a) Output is true 0 to +12 Vdc (not ±6 V, not 0-15 V); (b) Source is single-ended with shared 0 V reference to the S7-1200 system ground, OR isolated and willing to provide its own reference; (c) Source impedance should be ≤ 1 kΩ for accurate voltage division, ideally ≤ 100 Ω.
4. Resistor components on hand. At minimum: R1 (high-side) and R2 (low-side) precision metal-film resistors at the chosen ratio, matched to within the desired tolerance; 0.25 W rating or higher; optional 100 nF X7R ceramic across R2 for noise filtering.
5. Calibration reference. A bench multimeter accurate to > 0.1 % (e.g., Fluke 87V, Keithley DMM6500) and an adjustable 0-12 Vdc source or a precision voltage reference.

Voltage Divider Theory

A resistive voltage divider presents two series resistors between the source voltage and the module ground. The output, taken at the node between the resistors, follows:

V_out = V_in · R2 / (R1 + R2)

To step 12 Vdc down to 10 Vdc at full scale, we need V_out / V_in = 10/12 = 5/6. Therefore the resistor ratio is:

R2 / (R1 + R2) = 5/6

Solving:

6 · R2 = 5 · R1 + 5 · R2   ⇒   R2 = 5 · R1   ⇒   R1 : R2 = 1 : 5

This confirms the 6 : 5 ratio in head-of-line voltage terms (a 6-unit drop across R1, 5 across R2) and the 1 : 5 ratio in resistance. The choice of absolute resistor values determines loading error, current draw, and noise immunity.

Worked Example Using Standard E96 Values

Choosing R1 = 20 kΩ gives R2 = 100 kΩ, both well within the E96 (1 %) standard series. The divider ratio and resultant behavior are:

The current drawn from the source is:

I_total = V_in / (R1 + R2) = 12 / 120 000 = 100 µA

Power dissipation in each resistor:

P_R1 = (V_in - V_out)² / R1 = 4 / 20 000 = 200 µW
P_R2 = V_out² / R2 = 100 / 100 000 = 1 mW

A standard 0.25 W resistor is approximately 250× over-rated — heat is not a concern. Power rating matters less than stability, tolerance, and voltage coefficient for a divider.

Loading Error Caused by SM 1231 Input Impedance

The SM 1231 voltage channel does not present an open circuit; its differential input impedance (≥ 100 kΩ) appears in parallel with R2 of the divider, creating a Thevenin-equivalent load that shifts the divider ratio.

Letting Z_in = 100 kΩ (worst-case minimum), R1 = 20 kΩ, R2_nominal = 100 kΩ:

R2_effective = R2 ∥ Z_in = (100 × 100) / (100 + 100) = 50 kΩ

The effective divider ratio becomes:

V_out = 12 · (50) / (20 + 50) = 8.571 V  instead of 10.000 V

That is a 14.3 % gain error — far too large for production use. The fix is to make R_eff << Z_in. Three acceptable approaches:

Approach A — Low-impedance divider with a buffer op-amp. Use R1 = 200 Ω, R2 = 1000 Ω and drive the SM 1231 through an op-amp voltage follower (LM358, TL072, OPA2227). Even with Z_in = 100 kΩ, the loading error becomes < 0.005 %.

Approach B — Precision divider network. Buy a single 1 kΩ / 5 kΩ precision divider module (Caddock, VPG Foil, Precision Resistor Co.) specified to ±0.01 % ratio tolerance, 0.1 ppm/°C TC, and time stability < 50 ppm/year. Loading error with a 20 kΩ SM 1231 input is acceptably small.

Approach C — Tolerance scale-down. Multiply every resistor value by 0.1× (R1 = 2 kΩ, R2 = 10 kΩ). Current draw rises to 1 mA, still safe. Loading error is 10× smaller (~1.4 %) — large enough to require software calibration.

Step-by-Step Wiring Procedure

Step 1 — Identify the Correct SM 1231 Channel Terminals

The 6ES7231-4HD30-0XB0 (4 AI, 13 bit) terminal layout is shown in the S7-1200 System Manual. Each channel pair occupies four terminals arranged as follows for a single-ended voltage connection:

Refer to the SM 1231 wiring diagram in the S7-1200 system manual for the exact terminal layout of your catalog variant.

Step 2 — Build the Voltage Divider Off-Panel

Use a small terminal block or sealed potted divider module to mount R1 and R2. Keep lead lengths short. Wire:

1. One end of R1 to the transducer's +12 V signal terminal.
2. The junction of R1 and R2 (the divided node) to the SM 1231 M+ terminal.
3. One end of R2 to the same common ground as the SM 1231 Mana terminal and the transducer's 0 V return.
4. The 0 V return of the transducer must connect to the S7-1200 analog ground; floating source return will inject common-mode noise.

Step 3 — Add Filtering (Recommended)

A 100 nF X7R 50 V ceramic capacitor across R2 (between the divided node and ground) forms an RC low-pass filter with R1 ∥ R2 (Thevenin resistance). For R1 = 20 kΩ, R2 = 100 kΩ, R_th = R1 ∥ R2 = 16.67 kΩ and C = 100 nF:

f_c = 1 / (2π · R_th · C) = 1 / (2π · 16 667 · 100×10^-9) = ~95 Hz

Add a series 10 Ω resistor at the SM 1231 M+ terminal to damp any capacitive-driven oscillation with the ADC sampling input — good practice for any external divider feeding an SM 1231.

Step 4 — Wire the Shield

Use shielded twisted-pair cable from the divider output to the SM 1231 terminal. Connect the shield at one end only — the analog-ground (Mana) end — to avoid ground loops.

Step 5 — Configure the Input in TIA Portal

1. Open the project in TIA Portal V15 or later.
2. Open Device View and select the SM 1231 module.
3. In the Properties pane, expand "Analog inputs".
4. For the chosen channel, set: Measurement type = Voltage; Voltage range = 0 to 10 V (or ±10 V if your variant supports only bipolar); Integration time / smoothing = configure to match your noise environment.
5. Confirm the I/O address (default IW64, IW66, IW68, IW70 depending on slot).

For official configuration options, see SM 1231 Analog Input Module in the TIA Portal documentation.

Step 6 — Read the Raw Input

In OB1 or a cyclic OB, read the input word. The S7-1200 normalization for a 0-10 V channel produces raw counts from 0 (at 0 V) to +27648 (at 10.0 V). A ±10 V bipolar channel produces -27648 to +27648.

// Structured Text
iwRaw := "SM1231_1_AI".AI[0];

Step 7 — Apply Software Scaling to Recover 0-12 Vdc Engineering Units

Even with a perfect 1:5 divider, the SM 1231 reads 0 at 0 V and +27648 at exactly 10 V. Scaling 0-10 V → 0-12 Vdc engineering units in structured text:

// Convert raw 0-27648 to 0-12 Vdc with linear scaling
// V_divided = Raw / 27648 * 10 V
// V_engineering = V_divided * (12 / 10) = Raw * 12 / 27648
IF "SM1231_1_AI".AI[0] > 27648 THEN
    "V_ENG" := 12.0;
ELSIF "SM1231_1_AI".AI[0] < 0 THEN
    "V_ENG" := 0.0;
ELSE
    "V_ENG" := INT_TO_REAL("SM1231_1_AI".AI[0]) * 12.0 / 27648.0;
END_IF;

In Ladder (LAD), scale the raw value with the CALCULATE box configured for: OUT = (IN / 27648) × 12.0. This converts SM 1231 raw counts back to the original 0-12 Vdc transducer scale.

TIA Portal Configuration Reference

The configuration byte for each SM 1231 channel sets measurement type and range. The general structure (consult your firmware documentation for exact byte values):

Alternative Signal Conditioning Methods

A discrete resistor divider is the cheapest solution but is rarely the most accurate. For production or process-control applications where accuracy, temperature stability, and noise rejection matter, select one of the alternatives below.

1. Precision Resistor Divider Module

Buy a calibrated divider module from a precision-resistor vendor. Specify:

• Ratio: 5/6 (outputs 10 V from 12 V input)
• Ratio tolerance: ±0.01 % or tighter
• Absolute TCR: ≤ 5 ppm/°C
• Power rating: ≥ 50 mW

Mount in a shielded enclosure near the SM 1231 terminals.

2. Zener-Diode Voltage Reference

A 9.1 V or 10 V Zener diode (ON Semi BZX84C9V1LT1G, 1N4730A) in series with a current-limiting resistor from the 12 V source forms a temperature-trimmed clamp:

12V INPUT ---[ 100Ω ]--- node (Zener anode) ---[ 9.1V Zener to GND ]--- output ---> SM 1231 M+

The Zener must always be in its breakdown region, so size the series resistor such that even at 9 V transducer minimum, the Zener has ≥ 5 mA quiescent current. Drawback: non-linear V/I curve, Zener voltage temperature dependence (~±2 mV/°C for a quality 1N4730), and clamp-mode behavior make it a protection device more than a scaling device.

3. Op-Amp Buffer and Attenuator

Use an instrumentation amplifier or a non-inverting op-amp circuit to scale and buffer:

• Input divider (R1, R2, ratio 5:1) provides attenuation.
• Op-amp (TI OPA2227, Analog Devices AD8628) wired as voltage follower (gain = 1) presents an extremely low output impedance (< 0.001 Ω) to the SM 1231.
• Eliminates loading error entirely.
• Improves noise immunity through op-amp's low-Z drive.

For maximum noise rejection, use a true differential amplifier (INA128, AD620) and translate the 12 V source into a true ±10 V differential signal that the SM 1231 reads natively as a bipolar measurement.

4. Dedicated Signal Conditioner

Several manufacturers offer 12 V to 10 V isolated signal conditioners in DIN-rail form factors:

These provide galvanic isolation, ±0.1 % accuracy, and 1500 V isolation between field and S7-1200 — recommended for any high-side transducer that cannot share ground with the PLC.

5. Voltage-Reference Transducer

Use a precision 12 V → 10 V transducer IC such as a Texas Instruments REF102 (10 V reference) plus an op-amp follower. Build only if you have a clean reference supply.

6. Select a Different SM 1231 Channel Range

Some SM 1231 catalog variants support a wider voltage range configuration (e.g., ±10 V on 16-bit variants). For an input that genuinely exceeds ±10 V, look at the SM 1231 AI 4×16 bit (6ES7231-5ND30-0XB0) and check whether the firmware supports an extended-range option (it does not, by default — the maximum is ±10 V on all variants).

Verification and Calibration Procedure

After installing the divider, execute this 7-step validation:

1. Power off the S7-1200 before making any field wiring changes. Re-apply power only after all terminals are secured.
2. Source check. Apply 0.000 V from a calibration source. Read the SM 1231 raw value. Expect raw ≈ 0 ± 10 counts, scaled engineering value ≈ 0.000 V ± 0.005 V.
3. Mid-scale check. Apply 6.000 V from the calibration source. Expect raw ≈ 13824 (half of 27648), scaled engineering value ≈ 6.000 V ± 0.010 V depending on resistor tolerance.
4. Full-scale check. Apply 12.000 V from the calibration source. Expect raw ≈ 27648, scaled engineering value ≈ 12.000 V ± 0.020 V.
5. Compute gain correction at full scale. If the scaled reading deviates from 12.000 V by more than 0.05 %, calculate a one-point correction: new_scaled = (old_scaled / actual_at_full_scale_input) × desired_full_scale_value.
6. Compute offset at zero. Apply 0 V and read. If non-zero, subtract the offset in software. Derive the offset from a recent zero-scale measurement rather than fixing it at firmware level.
7. Temperature cycle. Enclose the divider assembly and ramp the operating temperature through the rated range (e.g., 0 °C → 60 °C over 4 hours). Confirm the full-scale reading drifts ≤ 0.05 % over the cycle; if not, replace the divider with a precision part.

Troubleshooting Matrix

Field Engineering Notes

Input Protection

The SM 1231 survives ±35 V continuous on voltage channels per the Siemens datasheet, but operating close to 12 V with a mis-wired divider could exceed the absolute maximum if the divider fails open. Add a transient voltage suppressor (TVS) of 10 V working voltage across the M+ / M- terminals of the SM 1231 to clamp any over-voltage event before it reaches the input pin. A Littelfuse SMBJ10CA surface-mount TVS or a leaded P6KE10A is a good choice.

Shielding and Common Mode

When the source and S7-1200 share a 0 V reference, the differential SM 1231 input measures only the desired 0-12 V across M+ to M-. Any common-mode voltage (e.g., from ground loops in a distant transducer) must be ≤ 4 V referenced to S7-1200 Mana to remain within the SM 1231 common-mode range. If the source floats, tie the source 0 V return to the S7-1200 Mana terminal at the panel only.

Why a Two-Point Calibration Beats a One-Point Calibration

With 1 % resistors, a one-point software gain calibration removes the systematic gain error at one point but leaves the temperature-dependent error uncorrected. For tighter performance, perform a two-point calibration: zero (apply 0 V) and span (apply 12 V) at the same operating temperature. Higher-grade precision resistors (0.01 % 0.1 ppm/°C) require only the manufacturer's published ratio — periodic two-point calibration is for the ADC and offset only.

SM 1231 Hardware vs SB 1231 Signal Boards

Where the SM 1231 is an external signal module on the S7-1200 bus, the SB 1231 is a signal board that plugs directly into the CPU front face. Voltage range options and resolutions are similar but limited to 1 AI (SB) vs 4 or 8 AI (SM). The same voltage-divider principles apply to both.

Cross-Platform Note: Allen-Bradley, Schneider, ABB

If your panel mixes PLC brands, the same 6:5 divider principle works on Allen-Bradley 1769-IF4 (MicroLogix/CompactLogix) which natively supports ±10 V and 0-10 V; on Schneider Electric TM3AI4 (Modicon M340/M221 ecosystem) which supports 0-10 V and ±10 V; and on ABB AI523 (AC500 family) which uses the same ±10 V default. Only the absolute resistor values might shift slightly to remain below the platform-specific input impedance minimum — verify the platform's voltage-mode input impedance in its datasheet before re-using a divider designed for SM 1231.

Common Mistakes to Avoid

1. Selecting resistor values 10× too high. The total divider impedance should be < 1/20 of the SM 1231 input impedance — otherwise loading error dominates. For a 100 kΩ SM 1231 input, R1 ∥ R2 should be ≤ 5 kΩ.
2. Forgetting to scale the raw counts back to the transducer's native range. Always multiply the SM 1231 raw voltage by the inverse of the divider ratio (12/10 = 1.2) in software.
3. Wiring the wrong polarity. SM 1231 accepts ±10 V, but a 0-12 V single-ended source becomes negative-going if M+ and M- are swapped.
4. Not removing the unused-voltage-channel requirement. The S7-1200 system manual requires shorting M+ to M- on every unused voltage channel. Failure to do so causes a noisy floating input.
5. Sharing a divider with more than one input. A passive divider cannot drive more than one SM 1231 channel cleanly. Use a buffer op-amp if multiple reads are required.

Conclusion

Connecting a 0-12 Vdc source to an SM 1231 0-10 Vdc analog input is straightforward using a 1:5 resistor divider, provided the divider's Thevenin resistance is far below the SM 1231 input impedance (≥ 100 kΩ) to avoid loading error, the resistors are well-matched with low TC and adequate tolerance, the system 0 V reference is properly commoned with the SM 1231 Mana terminal, and the software scales the raw count back to the 12 V span.

Where accuracy, isolation, and temperature stability matter — which is most process-control applications — replace the passive divider with a precision divider network, an op-amp buffered divider, or a dedicated DIN-rail signal conditioner from Phoenix Contact, Wago, or Knick. Always validate with a 0 / 6 / 12 V reference sweep and document the residual error budget.

FAQ