SM 1232 Sinusoidal Output: Maximum Frequency on S7-1200 PLCs

SM 1232 Sinusoidal Output: Maximum Frequency on S7-1200 PLCs

The Siemens SM 1232 analog output signal board/module is widely deployed in S7-1200 systems for proportional valve control, variable-speed drive reference signals, chart recorder emulation, and laboratory-style excitation. When the application demands a continuous sinusoidal waveform (for example, driving a pneumatic proportional valve with a 1 Hz to 50 Hz dither signal), engineers routinely ask: what is the highest frequency a SM 1232 can reproduce? The answer is bounded by three independent limits: the analog output stage's settling time, the CPU's OB3x cyclic interrupt granularity, and the resulting deterministic jitter in the time domain. This reference walks through each constraint with the formulas, parameter tables, structured-text code, and verification checks required for a production-grade implementation.

1. SM 1232 Analog Output Hardware Overview

The SM 1232 is the analog output companion to the digital SM 1223 modules. Two form factors exist:

For sinusoidal generation, the dominant hardware constraint is the output settling time — the time required for the DAC output to reach 95 % of the programmed value after a step change. This single parameter defines the maximum useful step rate of the analog channel and therefore the upper bound on sinusoidal frequency.

2. Analog Output Settling Time Specifications

Per the S7-1200 System Manual (06/2015), the SM 1232 output stage settling time depends on the output type and the connected load:

From these values, derive the maximum step rate. For a 0-to-10 V output driving a resistive or lightly capacitive load (typical valve command or drive reference), each analog update must be at least:

t_step ≥ 750 µs (worst-case voltage)

t_step ≥ 2 ms (worst-case current)

Reciprocally, the maximum step frequency f_step_max equals:

f_step_max = 1 / t_step

For a voltage-output SM 1232 with a 1 µF load:

f_step_max = 1 / 750 µs = 1 333 steps/s

For a current-output SM 1232 with a 10 mH load (worst case):

f_step_max = 1 / 2 ms = 500 steps/s

3. Sine Sampling Theory and the Nyquist Limit

A continuous sinusoid is fully described by its amplitude, frequency, and phase. To reconstruct it from a staircase waveform, the staircase must contain enough samples per period so the reconstruction error is bounded. Per the Nyquist–Shannon sampling theorem:

f_s ≥ 2 · f_signal

Two samples per period only preserve the sinusoid's identity; they cannot reproduce its shape faithfully. In practice, a sinusoidal reconstruction requires 10 to 32 samples per period for < 1 % THD (total harmonic distortion) at the analog output. The number of samples per period is:

N = f_s / f_signal

Combined with the settling-time ceiling, the highest sine frequency the SM 1232 can output at N samples per period is:

f_signal_max = f_step_max / N

The practical envelope for a real-world proportional-valve or drive-reference use case (voltage output, capacitive load < 1 µF, N = 20) is roughly 50-66 Hz maximum sine frequency. Beyond that, THD rises rapidly because each staircase step exceeds the amplifier's settling-time envelope.

4. PLC Scan Cycle: Buffered I/O vs Direct (:P) Access

The S7-1200 maintains a process image of inputs (%I) and outputs (%Q). During OB1, the program reads input values from the input process image (PII) captured at the start of the cycle and writes to the output process image (PIQ) which is flushed to the physical outputs at the end of the cycle. This buffering is fundamental to deterministic ladder logic execution but introduces a one-cycle latency on every analog update.

For high-rate analog output, S7-1200 supports direct (immediate) access via the :P suffix:

• %QW0:P — writes directly to the physical output register, bypassing the PIQ.
• %IW0:P — reads the current physical input register, bypassing the PII.

The :P qualifier forces the I/O update at the instant the instruction executes, eliminating the end-of-cycle PIQ flush delay. For sinusoidal generation, this is critical: without :P, every analog step is delayed by one full OB1 scan, smearing the waveform in time.

5. OB3x Cyclic Interrupt Configuration

S7-1200 CPUs (firmware V4.0 and later) support eight cyclic interrupt OBs: OB30 through OB38. Each can be assigned an independent scan period (1 ms to 60 000 ms) and a phase offset. The recommended pattern for sinusoidal generation:

1. Set the OB3x cycle time T_OB equal to the desired sample interval 1 / f_s.
2. Place the DAC-write logic inside the OB.
3. Use :P direct writes for the analog output to skip the PIQ.
4. Maintain a phase index (angle accumulator) in a static tag of an instance DB.

The 1 ms floor is dictated by the S7-1200 cyclic-interrupt granularity. CPUs in the 1211C / 1212C range may not sustain a 1 ms OB30 while servicing PROFINET, web server, and HMI polling; the 1215C and 1217C have headroom.

6. Determinism and Jitter Analysis

A PLC is not a DSP. The cyclic interrupt will be preempted by higher-priority OBs (OB82 diagnostic, OB121 programming error, OB80 timeout, OB91 startup) and delayed by:

• PROFINET / PROFIBUS I/O update (typically 0.5-2 ms).
• HMI / OPC UA polling on the PN interface.
• Web server GET requests.
• Open User Communication (TSEND/TRCV) handshakes.

The resulting jitter appears as phase noise on the sinusoid. To measure jitter in OB3x:

1. Read the system clock RD_SYS_T at the top of the OB.
2. Subtract the previous sample's timestamp.
3. Compare to T_OB; deviations > 50 µs accumulate as visible jitter on the analog output.

If jitter exceeds 1 % of the period, two compensation strategies are available:

• Phase compensation: Use the measured elapsed time to advance the angle accumulator proportionally to the actual interval rather than the nominal interval.
• Phase-locked loop (PLL): Lock the OB3x phase to a hardware timer or external interrupt.

7. Structured Text Implementation (SCL)

The following SCL block generates a sinusoid on channel 0 of an SM 1232, assuming the SM is at logical slot 0 (output address %QW96 typically, depending on configuration). Place this inside OB30 with a 2 ms cycle for a 50 Hz / 100-sample signal.

FUNCTION_BLOCK FB_SineGen
VAR
    Angle        : REAL;    // 0..2*PI accumulator
    Step         : REAL;    // 2*PI * f_signal * T_OB
    Amplitude    : REAL;    // peak amplitude in engineering units (e.g., 27648 = 10 V)
    Offset       : REAL;    // DC offset for unipolar outputs
    SamplesPerSec: REAL;    // 1 / T_OB
END_VAR
BEGIN
    // --- Step 1: advance the angle accumulator ---
    Angle := Angle + Step;
    IF Angle >= 6.2831853 THEN
        Angle := Angle - 6.2831853;
    END_IF;

    // --- Step 2: compute sine value scaled to DAC range ---
    // For bipolar ±10 V output:
    //   output = Offset + Amplitude * SIN(Angle)
    // For unipolar 0-10 V output:
    //   output = Offset + Amplitude * (SIN(Angle) + 1) / 2
    %QW96:P := REAL_TO_INT(Offset + Amplitude * SIN(Angle));
END_FUNCTION_BLOCK

Configure OB30 properties in TIA Portal:

• Cycle time: 2 ms
1
• Phase offset: 0 µs
• Priority: Leave default (typically priority class 8).
• Assigned FB: instance DB of FB_SineGen.

To change the signal frequency at runtime without restarting OB30, update the Step tag:

Step = 2π · f_signal · T_OB = 2π · f_signal / f_s

For a 50 Hz signal at 2 ms sample time:

Step = 2π · 50 · 0.002 = 0.6283 rad/sample

8. Ladder Logic Alternative

If the project standard mandates LAD/FBD, the same functionality is achievable using:

• A MOVE instruction writing the computed INT to %QW96:P.
• An ADD_R chain in the angle accumulator.
• The built-in SIN instruction from the "Extended Instructions" palette (S7-1200 firmware V4.0+).

The execution time of the SCL SIN function on a CPU 1215C is approximately 18-25 µs — well below the 2 ms OB30 budget — but if the cycle time is set to 1 ms, the sine call may consume 2-3 % of CPU time per OB30 invocation. Benchmark on the target CPU before committing to 1 ms sampling.

9. PWM and PTO as Alternative Analog Reconstruction

If the S7-1200 must drive a slow actuator and the cosine fidelity requirement is modest (< 5 % THD), consider modulating a digital high-speed output:

• PWM (Pulse Width Modulation): The CPU's onboard PWM generators (up to 4 on a CPU 1215C) produce a fixed-frequency, variable-duty-cycle square wave. Feed this through an external RC low-pass filter; the DC component reconstructs the average value. Filter cutoff must be at least 10× below the PWM carrier to suppress ripple.
• PTO (Pulse Train Output): The high-speed counters can emit a fixed number of pulses at a programmed frequency; combine with an external integrator (op-amp with C in feedback) for an analog ramp. Not directly suitable for sinusoidal reconstruction but useful as a coarse D/A.

For sinusoidal reconstruction, PWM is the most viable PLC-native approach. A 1 kHz PWM with a 100 Hz cutoff RC filter gives ~5 % ripple, which can be acceptable for dither signals but inadequate for instrumentation.

10. External Signal Generator Considerations

When the application demands > 100 Hz sine fidelity (audio excitation, ultrasonic transducer drive, vibration table control), the PLC is the wrong tool. Specify a dedicated signal source:

• Function/Arbitrary Waveform Generator: Standalone instruments (Keysight 33500B, Rigol DG1000 series, Siglent SDG1000) produce 1 µHz to 30 MHz sine with < -60 dBc THD. Control them via Modbus TCP, RS-232, or USB from the S7-1200.
• DDS (Direct Digital Synthesis) IC: A small PCB module (AD9833, AD9850) generates 0-12.5 MHz sine from a serial SPI command. Suitable for embedded excitation where the PLC orchestrates but does not generate the waveform.
• CompactDAQ / PXIe: National Instruments multifunction DAQ (myDAQ, cDAQ-9174) provides up to 200 kHz analog output update rate with hardware-timed generation. Used for laboratory-grade signal synthesis.

11. Mechanical Alternatives for Sinusoidal Motion

If the ultimate goal is sinusoidal mechanical motion rather than a sinusoidal electrical signal, a mechanical cam or crank profile driven by a servo motor may produce a more accurate result than any electrical DAC. The crank's displacement is naturally sinusoidal; a single rotation of the crank at constant angular velocity yields a perfect sine stroke. Pair the crank with a SINAMICS V90 or SIMOTION D servo drive for closed-loop positioning, then synchronize the master axis via PROFIdrive / PROFINET IRT.

This is the preferred architecture when driving pneumatic servo valves whose spool position must follow a sinusoid (for example, in active vibration damping or respiratory simulator pumps).

12. Verification and Commissioning Procedure

1. Verify wiring: Connect the SM 1232 voltage output channel 0 to an oscilloscope with a 10:1 probe and a shielded twisted pair.
2. Set the engineering range: In the device configuration, choose "Voltage ±10 V" and confirm the corresponding INT range -27648 to +27648.
3. Force the OB30 frequency: Set f_signal = 1 Hz first; verify the scope shows a clean sinusoid with peak-to-peak amplitude matching 2 · Amplitude.
4. Verify timing: Use the scope's horizontal cursors to confirm period T = 1 / f_signal ± 2 %.
5. Step frequency up: Sweep 1, 5, 10, 25, 50, 75, 100 Hz. At each step, measure peak-to-peak and THD.
6. Watch for ripple: Visible staircase artefacts appear when the OB30 interval approaches the SM 1232 settling time. Reduce N or move to a CPU with faster interrupt.
7. CPU load check: Open TIA Portal online > Diagnostics > CPU information. OB30 time must stay < 80 % of cycle time; otherwise reduce cycle time or move logic to OB1.
8. Jitter probe: Place an empty FB in OB30 that increments a tag and a second tag that captures RD_SYS_T each call. Diff in the watch table to measure actual interval.

13. Troubleshooting Matrix

14. S7-1200 CPU Model Selection for Sine Generation

15. Frequently Asked Questions