STEP 7 Micro/WIN V2.1 Technical Reference for Legacy S7-200 PLCs
This reference consolidates the engineering knowledge required to deploy, program, troubleshoot, and migrate SIMATIC S7-200 systems built on STEP 7 Micro/WIN V2.1. It targets support engineers, retrofitters, and integrators who must service machines still controlled by S7-200 CPUs (CPU 212 through CPU 226) and who need a controlled migration path to either STEP 7 Micro/WIN SMART or TIA Portal without disturbing the running process.
Overview and Purpose
STEP 7 Micro/WIN V2.1 is the final service release in the classic 32-bit programming environment dedicated to the SIMATIC S7-200 micro-PLC family. Issued as the V2.0 → V2.1 update, it delivered functional enhancements, new wizards, and stability fixes on top of Micro/WIN V2.0 while remaining fully backward-compatible with every project written under earlier V2.x releases. The package replaced the legacy STEP 7 Micro/DOS and the 16-bit Micro/WIN V1.x toolchains and standardized the workflow that survives, in modified form, in today's STEP 7 Micro/WIN V2.1 update package and in the subsequent STEP 7 Micro/WIN SMART tool for the S7-200 SMART CPU.
Micro/WIN V2.1 edits three IEC 61131-3 graphical and textual languages (LAD, FBD, STL), integrates the instruction library wizards (PID, USS, Modbus RTU master, recipe, data log), and provides the system block editors for the S7-200 special memory (SM), interrupts, high-speed counters, and communication ports. It also includes the PC/PPI and USB/PPI cable drivers and the freeport protocol test terminal that an integrator needs when commissioning an S7-200 serial network.
Version Evolution: Micro/WIN V2.0 → V2.1
Siemens formally published the V2.1 release as a successor to V2.0. According to the official Siemens support entry "STEP 7 Micro/WIN - New Version 2.0", the V2.0 baseline introduced compatibility with every previous Micro/WIN project, the new CPU 224XP and CPU 226 firmware families, and the first revisions of the PID and USS instruction wizards. The follow-up V2.1 update entry documents the additional wizards, library blocks, and bug fixes that complete the V2.x line.
| Feature | Micro/WIN V2.0 | Micro/WIN V2.1 |
|---|---|---|
| Backward-compatible project import from V1.x | Yes | Yes |
| CPU 224XP / CPU 226 firmware support | Yes (initial) | Yes (expanded) |
| PID auto-tune wizard (8-loop) | Yes | Yes, with new tuning tables |
| USS protocol instruction library | Yes | Yes, with extended drive list |
| Modbus RTU master library (pre-V2.1 shipped as add-on) | Optional | Integrated |
| Recipe and Data Log wizards | Yes | Yes, with export to CSV |
| Freeport ASCII test terminal | Yes | Yes, improved buffer handling |
| CP 243-1 Ethernet wizard | Yes | Yes |
| CP 243-2 AS-Interface wizard | Add-on | Integrated |
| Windows XP / 2000 native install | Yes | Yes |
| Windows 7 / 10 compatibility (32-bit only) | Limited | Limited (legacy MSI) |
There is no "V2.2" release; V2.1 is the terminal release of the classic toolchain. Once a customer migrates an S7-200 to the S7-200 SMART CPU, the programming environment becomes STEP 7 Micro/WIN SMART, not a newer version of Micro/WIN V2.x.
System Requirements and Installation
Micro/WIN V2.1 was engineered for the Microsoft Windows 2000 / XP era. It will install and run on Windows 7 32-bit with administrator rights, but it does not ship a Windows 10 / 11 native installer and will not install on 64-bit only editions without compatibility shims. The official Siemens position is documented through the SiePortal thread "Downloading STEP 7- MICRO/WIN SMART SOFTWARE", which clarifies the current SiePortal position on legacy Micro/WIN distribution and recommends that integrators pivot to Micro/WIN SMART for ongoing development.
| Parameter | Minimum | Recommended |
|---|---|---|
| Operating system | Windows 2000 SP4 / XP SP2 | Windows XP SP3 32-bit |
| CPU | Intel Pentium 300 MHz | Intel Pentium III 800 MHz |
| RAM | 128 MB | 256 MB |
| Free disk | 200 MB | 500 MB |
| Display | 800 × 600, 256 colors | 1024 × 768, 16-bit |
| Serial / USB | RS-232 COM port or USB 1.1 | Dedicated RS-232 (COM1/COM2) |
| Required runtime | Microsoft .NET not required; native Win32 | |
Standard install procedure:
- Verify the operating system and that the user has administrative rights.
- Mount or insert the official Siemens installation media (or run the signed setup.exe downloaded from SiePortal).
- Select Install STEP 7 Micro/WIN V2.1 and accept the license terms.
- When prompted, install the PC/PPI cable driver for either the RS-232 (6ES7 901-3CB30-0XA0) or the USB (6ES7 901-3DB30-0XA0) variant.
- Reboot if Windows requests it.
- Launch Micro/WIN, open Tools → PC/PPI Cable → PPI, set the active COM port and baud rate (default 9.6 kbps for legacy CPUs, 19.2 kbps for newer firmware).
S7-200 CPU Compatibility Matrix
Micro/WIN V2.1 supports every S7-200 CPU that Siemens produced, from the earliest CPU 212 to the terminal CPU 226. Use the following table to match part numbers to firmware families before opening the project.
| CPU | MLFB (example) | On-board DI / DO | AI / AO | Program / Data | Max expansion modules | Port count |
|---|---|---|---|---|---|---|
| CPU 212 | 6ES7 212-1AA01-0XB0 | 8 / 6 | 0 / 0 | 1 KB / 512 B | 2 | 1 (PPI/Freeport) |
| CPU 214 | 6ES7 214-1AC01-0XB0 | 14 / 10 | 0 / 0 | 4 KB / 2 KB | 7 | 1 (PPI/Freeport) |
| CPU 215 | 6ES7 215-1AD01-0XB0 | 14 / 10 | 0 / 0 | 4 KB / 2 KB | 7 | 2 (PPI/MPI/Freeport) |
| CPU 216 | 6ES7 216-1AD01-0XB0 | 24 / 16 | 0 / 0 | 8 KB / 2.5 KB | 7 | 2 (PPI/MPI/Freeport) |
| CPU 221 | 6ES7 211-0BA23-0XB0 | 6 / 4 | 0 / 0 | 4 KB / 2 KB | 0 | 1 (PPI/Freeport) |
| CPU 222 | 6ES7 212-1AB23-0XB0 | 8 / 6 | 0 / 0 | 4 KB / 2 KB | 2 | 1 (PPI/Freeport) |
| CPU 224 | 6ES7 214-1AD23-0XB0 | 14 / 10 | 0 / 0 | 8 / 12 KB / 8 KB | 7 | 1 (PPI/Freeport) |
| CPU 224XP | 6ES7 214-2AD23-0XB0 | 14 / 10 | 2 / 1 | 12 / 16 KB / 10 KB | 7 | 2 (PPI/Freeport) |
| CPU 226 | 6ES7 216-2AD23-0XB0 | 24 / 16 | 0 / 0 | 16 / 24 KB / 10 KB | 7 | 2 (PPI/Freeport) |
...23-0XB0) ship with newer firmware that supports the expanded program/data memory and the 187.5 kbps PPI baud rate. Older 21 or 01 suffix CPUs do not accept Micro/WIN V2.1 project blocks compiled with the newer firmware instruction set. Always cross-check the MLFB suffix against the CPU nameplate before downloading.Memory Architecture and Address Map
The S7-200 maps all I/O, flags, timers, counters, and data into a single byte-and-bit address space accessible by mnemonic syntax inside LAD, FBD, and STL. Micro/WIN V2.1 enforces the address ranges; the programmer cannot declare out-of-range operands.
| Area | Prefix | Size | Access | Notes |
|---|---|---|---|---|
| Process image input | I | 0.0 – 31.7 (max, CPU dependent) | Bit / Byte / Word / DWord | Read-only, refreshed at scan start |
| Process image output | Q | 0.0 – 31.7 (max) | Bit / Byte / Word / DWord | Read/Write, written at scan end |
| Bit memory | M | 0.0 – 31.7 (256 bits typical) | Bit / Byte / Word / DWord | Volatile, retained only if configured |
| Variable memory | V | 0 – 10239 (CPU dependent) | Byte / Word / DWord | Primary data store; retained range configurable |
| Special memory | SM | 0 – 549 (CPU dependent) | Bit / Byte / Word / DWord | Diagnostic, clock, HSC, freeport, interrupts |
| Timers | T | 0 – 255 | Bit (contact) / Word (preset/current) | 1 ms, 10 ms, 100 ms resolutions |
| Counters | C | 0 – 255 | Bit (contact) / Word (preset/current) | CTU, CTD, CTUD |
| High-speed counters | HC | 0 – 5 | DWord only | Read-only, hardware-driven |
| Analog inputs | AIW | 0 – 62 (word-aligned) | Word only | 0 – 10 V or 0 – 20 mA |
| Analog outputs | AQW | 0 – 62 (word-aligned) | Word only | ±10 V or 0 – 20 mA |
| Accumulators | AC | 0 – 3 | Byte / Word / DWord | Scratchpad; no retentivity |
| Local / expansion | L | 0.0 – 59.7 | Bit / Byte / Word / DWord | Per-POU scope, not retentive |
Retentivity is configured in the System Block dialog. By default, the V memory region below the configured boundary is retained across power cycles; data above is volatile. For the CPU 224 / 224XP / 226, the default retentive V range is VB0 – VB511 and the default retentive timer range is T0 – T31, the default retentive counter range is C0 – C31.
Programming Languages
Micro/WIN V2.1 supports three IEC 61131-3 textual or graphical editors and a fourth "instruction list" view that can be enabled.
| Language | Editor | Use case | File extension |
|---|---|---|---|
| LAD (Ladder Diagram) | Graphical rung editor | Discrete logic, motor control, interlock networks | .lzp / .mwp |
| FBD (Function Block Diagram) | Graphical block editor | Analog loops, math, supervisory code | .fbd |
| STL (Statement List) | Textual assembler-style | Complex math, indirect addressing, conditional jumps | .stl |
| Instruction list view | Textual mnemonic | Power-user reading of compiled logic | View only |
A single POU (program organization unit) can mix STL and LAD/FBD sub-routines; cross-language calls are allowed. STL provides the indirect addressing through &VBxx (address-of) and *VDxx (pointer) operators that are required for recipe indexing and Modbus table walks.
Communication Interfaces and Cables
The S7-200 CPU exposes one or two onboard RS-485 ports that can operate in PPI, MPI, or Freeport mode. The communication wizard in Micro/WIN V2.1 generates the configuration subroutine (USR_INIT, USR_SBR_x) for each protocol. The most common field configurations are summarized below.
| Protocol | Typical baud rate | Topology | Use case | Max stations |
|---|---|---|---|---|
| PPI (Point-to-Point) | 9.6 kbps / 19.2 kbps | Multi-drop RS-485 | Programming, HMI, peer-to-peer | 32 per segment |
| PPI high-speed | 187.5 kbps | Multi-drop RS-485 | Higher throughput peer-to-peer | 32 per segment |
| MPI (Multi-Point) | 187.5 kbps | Multi-drop RS-485 | S7-200 ↔ S7-300/400 data exchange | 32 per segment |
| Freeport | 1.2 – 115.2 kbps | Point-to-point RS-485 / RS-232 | ASCII / RTU to third-party devices | 1 master, 1 slave |
| USS | 1.2 – 19.2 kbps | Multi-drop RS-485 | Siemens Micromaster drives | 31 drives |
| Modbus RTU master (library) | 1.2 – 115.2 kbps | Multi-drop RS-485 | Modbus slaves | 247 per network |
| Ethernet via CP 243-1 | 10/100 Mbps | Star / LAN | S7 communication, OPC via PC Access | 1 connection / module |
| Ethernet via CP 243-1 IT | 10/100 Mbps | Star / LAN | E-mail, FTP, HTTP server | 1 connection / module |
Recommended cabling inventory for commissioning:
-
PC/PPI cable (RS-232):
6ES7 901-3CB30-0XA0— multi-master, switch-selectable PPI / PPI/Freeport. -
USB/PPI cable:
6ES7 901-3DB30-0XA0— USB 1.1, requires Siemens USB driver. -
Profibus connector:
6GK1 500-0EA02with terminating resistor switch for MPI trunks. -
RS-485 repeater:
6ES7 972-0AA01-0XA0for segment extension beyond 32 stations or 1 200 m.
PPI/MPI baud rate mismatch is the single most common field-connection fault. The CPU side is set in the System Block; the cable side is set by the rotary switch on the PC/PPI cable (positions 0 – 9 mapping to 1.2 – 115.2 kbps). When in doubt, default both sides to 9.6 kbps and re-attempt connection.
Upload, Download, and Verification Procedures
The classic field service flow on a running machine is: (1) confirm the CPU type, (2) upload the live program, (3) document the configuration, (4) edit offline, (5) download the modified program, (6) verify by comparing the online and offline blocks. Each step has a guardrail to prevent damage to the running process.
Pre-upload checklist
- Connect the PC/PPI or USB/PPI cable and confirm that the green RUN LED stays lit and the SF LED does not enter a new fault state when the cable is hot-plugged.
- In Micro/WIN, open Communications → Set PG/PC Interface and verify the cable is mapped to the correct COM port and PPI protocol.
- Open Communications → Read/Write CPU → Read CPU. The dialog will report the CPU model, firmware version, and current RUN/STOP state. Abort if the CPU is reporting a system fault.
- Select File → Upload to retrieve the project. Save to a versioned directory with the machine tag and date.
Download guardrails
- Place the CPU in STOP first; downloads of program blocks to a running CPU are permitted only with the "Run-mode edit" option, which is risk-bearing and must be enabled per change.
- Confirm the System Block (port configuration, retentive ranges, password) matches the existing CPU configuration, or upload it first.
- Download Program Block, then Data Block, then System Block, in that order.
- After download, perform Compare against the offline project before placing the CPU in RUN.
Verification matrix
| Check | Micro/WIN menu path | Pass criterion |
|---|---|---|
| CPU identification | Communications → Read/Write CPU | Reported MLFB matches nameplate |
| Scan time | Status Chart → SMW22 / SMW24 | Within machine envelope |
| Program compare | PLC → Compare | No block-level differences |
| Force state | Debug → Force | No unintended forces present |
| Retentive range | System Block → Retentive Ranges | Matches documented value |
| Passwords | System Block → Password | Documented; do not clear without authorization |
Diagnostics: SMB Bits and Error Codes
The Special Memory (SM) area provides the primary diagnostic channel. Micro/WIN V2.1 exposes SM bits through the Status Chart and as named symbols in the Symbol Table when the optional SM Symbol Library is imported.
| Address | Name | Function |
|---|---|---|
| SM0.0 | Always_On | 1 in every scan |
| SM0.1 | First_Scan_On | 1 in the first scan after power-up or STOP-to-RUN |
| SM0.3 | Retentive_Data_Lost | 1 if retentive data was lost (e.g. capacitor discharged) |
| SM0.4 | 1_Min_Clock | 30 s on / 30 s off |
| SM0.5 | 1_Sec_Clock | 0.5 s on / 0.5 s off |
| SM0.6 | Scan_Clock | Single-scan pulse |
| SM0.7 | RTM_Error | 1 if RTC error |
| SMW22 | Last_Scan_Time_ms | Scan time of the previous scan |
| SMW24 | Min_Scan_Time_ms | Minimum scan since STOP-to-RUN |
| SMW26 | Max_Scan_Time_ms | Maximum scan since STOP-to-RUN |
| SMB28 | Pot0_Value | Analog trim pot 0 (0 – 255) |
| SMB29 | Pot1_Value | Analog trim pot 1 (0 – 255) |
| SMB30 | Port0_Mode | Freeport / PPI protocol and baud for port 0 |
| SMB34 / SMB35 | Timed_Interrupt_0 / 1_Interval | 0 – 255 ms tick for INT_0 / INT_1 |
| SMB130 | Port1_Mode | Freeport / PPI protocol and baud for port 1 |
| SMB36 – SMB45 | HSC0_Control | Mode, direction, preset, current |
| SMB46 – SMB55 | HSC1_Control | Mode, direction, preset, current |
| SMB56 – SMB65 | HSC2_Control | Mode, direction, preset, current |
| SMB136 – SMB145 | HSC3_Control | Mode, direction, preset, current |
| SMB146 – SMB155 | HSC4_Control | Mode, direction, preset, current |
| SMB156 – SMB165 | HSC5_Control | Mode, direction, preset, current |
The SF (System Fault) LED behavior decodes as follows:
| SF LED | RUN LED | STOP LED | Likely meaning |
|---|---|---|---|
| Off | On | Off | Normal operation |
| Solid | Off | On | User programming error; read SM5.0 / SM4.x |
| Solid | Off | Flashing | Hardware fault; check SM31 / SMW100 |
| Flashing | On | Off | Non-fatal diagnostic (e.g. retentive data loss, SM0.3) |
| Off | Off | Off | No power or CPU has failed |
For analog I/O scaling, use the standard 0 – 10 V / 0 – 20 mA normalization. Micro/WIN V2.1 returns 0 – 32 000 for unipolar inputs and –32 000 to +32 000 for bipolar inputs, with the engineering range mapped by:
E = (R × (Emax – Emin) / 27 648) + Emin
where R is the raw AIW value and E is the engineering-scaled result. For bipolar ±10 V inputs the denominator is 27 648 and the offset is Emin; for 4 – 20 mA inputs, normalize against the 6 553 – 27 648 working range to preserve the 4 mA zero offset.
Migration to STEP 7 Micro/WIN SMART
When the S7-200 must be replaced by an S7-200 SMART CPU, the program must be ported. Micro/WIN V2.1 cannot download to an S7-200 SMART CPU; conversely, Micro/WIN SMART cannot open an original Micro/WIN V2.1 .mwp project. The migration is performed by manual import and re-wiring.
- In Micro/WIN V2.1, compile the project and export the symbol table to CSV (Symbol Table → Export) and the data block contents to CSV (Data Block → Export).
- Document the System Block configuration: port baud rates, station addresses, retentive ranges, passwords, and any CP 243-1 / CP 243-2 parameters. Take screenshots.
- Identify the new CPU model. The S7-200 SMART standard catalog includes CPU SR20, SR30, SR40, SR60, ST20, ST30, ST40, ST60.
- Open Micro/WIN SMART, recreate the symbol table by importing the CSV, and re-author the LAD/FBD/STL logic. Most bit, byte, word, math, and timer instructions port directly.
- Re-implement Freeport and USS communication; Micro/WIN SMART provides updated libraries (USS protocol instruction v2.0, Modbus RTU master v2.0).
- Compile, download to the new CPU in STOP, perform compare, and place in RUN.
Migration to TIA Portal
For end users standardizing on TIA Portal, Micro/WIN V2.1 projects must be re-authored by hand because TIA Portal does not include an S7-200 importer. The migration path uses a S7-200 SMART intermediate, then converts to TIA Portal via the TIA "Migrate project" wizard. Siemens publishes this workflow through SiePortal and the TIA Portal help system.
- Migrate the S7-200 project to an S7-200 SMART project as described in the previous section.
- In TIA Portal V20 (or current), select Project → Migrate project and open the exported SMART project file.
- Confirm the device version and accept the migration log; resolve any address conflicts flagged by the wizard.
- Replace proprietary S7-200 libraries (PID, USS, Modbus RTU master v1.x) with their TIA Portal equivalents in the S7-1500 / ET 200SP firmware.
- Validate by downloading to the new controller in STOP, performing compare, then placing the system in RUN with supervision.
Where a clean migration is not feasible (for example, very large V memory maps with indirect addressing), consider a controlled shutdown and parallel-run strategy that maintains the S7-200 as a backup controller behind a hard-wired transfer switch while the TIA Portal replacement is commissioned.
Troubleshooting Matrix
| Symptom | Likely root cause | Verification | Remediation |
|---|---|---|---|
| "Communications error" on Read CPU | Baud rate or address mismatch between CPU and cable | Compare CPU System Block station and baud against cable DIP / rotary switch | Set both sides to 9.6 kbps, retry; re-terminate RS-485 |
| SF LED solid after download | Indirect addressing or array out-of-range error | Read SM31 / SMW100 / SMB200 area; check STL indirect operators | Bound-check indices; recompile; re-download |
| CPU will not enter RUN | Output forced, password mismatch, or hardware fault | Debug → Force table; PLC → Clear → All Forces; check I/O wiring | Clear forces, re-cycle power, restore from project backup |
| Freeport receives garbage | Baud, parity, or stop bits mismatch with partner | SMB30 / SMB130 vs. partner settings | Match 8N1 / 8E1, retry |
| Analog input reads 32 767 | Input open-circuit or out-of-range | Verify 4 – 20 mA loop wiring and transmitter | Check loop supply, replace transmitter |
| Retentive data lost on power cycle | Capacitor discharged or retentive range not set | SM0.3 latched; System Block retentive range | Recharge capacitor 48 h; set retentive V range |
| USS drive responds erratically | Address or parity mismatch | USS_CTRL error byte (input parameter) | Match drive address (1 – 31); use 8E1; check termination |
| PID loop oscillates | Sample time too short for plant time constant | PID status byte / trend chart | Increase loop sample time; re-tune gains |
| Program compare fails after download | System Block, Data Block, or recipe data not downloaded | PLC → Compare → Show Differences | Download missing block type |
| Password required dialog blocks upload | CPU password set previously | System Block → Password | Provide authorized password; do not clear without owner consent |
Field-Engineering Notes
- Always keep an exported copy of the System Block screenshot and the symbol table alongside the source
.mwpfile; the System Block is not visible inside the program editor. - Document every PPI/MPI station address and baud rate on the cabinet drawing; this data is not retrievable from a lost project.
- Use the recipe and data log wizards to keep process constants out of the program body, simplifying future migration.
- Plan for the eventual migration to S7-200 SMART or TIA Portal now, even if the S7-200 is still healthy. Use the standardized project template as the bridge artifact.
- Capture live trends of the SMW22 / SMW24 / SMW26 scan-time registers when first commissioning; this becomes the baseline for future troubleshooting.
For ongoing industrial edge modernization, Siemens positions Industrial Edge as the successor architecture for data and software management on the shop floor. While Industrial Edge does not replace the S7-200 directly, it provides the data-hub architecture that new edge-deployed controllers integrate with, and it is the recommended next step beyond the S7-200 SMART migration.
FAQ
Where can STEP 7 Micro/WIN V2.1 be downloaded legally?
Micro/WIN V2.1 is distributed through Siemens' official SiePortal and legacy support channels (Siemens ID 4337507). It is not offered through public file-sharing services. If your organization cannot locate the package, open a ticket with Siemens Industrial Customer Support for licensing transfer.
Can Micro/WIN V2.1 download to an S7-200 SMART CPU?
No. The S7-200 SMART CPU family requires STEP 7 Micro/WIN SMART, which is a separate product. Program conversion is a manual re-authoring process; TIA Portal migration is performed through a S7-200 SMART intermediate stage.
What is the maximum PPI baud rate supported by the S7-200?
187.5 kbps with CPU 224 / 224XP / 226 firmware revision 23 and later, using the PC/PPI cable (6ES7 901-3CB30-0XA0) on a properly terminated RS-485 segment. Older CPU 212 / 214 / 215 / 216 units are limited to 19.2 kbps PPI.
Which cable do I need to program an S7-200 from a Windows 10 PC?
Use the USB/PPI cable (6ES7 901-3DB30-0XA0) and install the legacy Siemens USB driver. Run Micro/WIN in Windows 7 compatibility mode under an administrator account. For an RS-232 port use the 6ES7 901-3CB30-0XA0 PC/PPI cable.
How do I clear a forgotten CPU password on an S7-200?
The legitimate procedure is to contact Siemens support with proof of ownership and provide the CPU MLFB. Do not attempt unauthorized memory clearing; this can corrupt the project and violates Siemens' licensing terms.
How do I migrate an S7-200 PID loop to a S7-200 SMART or TIA Portal controller?
Capture the PID loop configuration (loop tag, setpoint, input, output, loop table) from Micro/WIN V2.1, export it to a CSV, and re-enter it into the destination tool's PID wizard. Auto-tuning must be re-run on the new hardware because plant time constants do not transfer.
What is the meaning of the SF LED flashing while RUN stays on?
A flashing SF LED with RUN on indicates a non-fatal diagnostic such as retentive data loss (SM0.3 = 1) or a battery / capacitor warning. Read the relevant SMB bits in the Status Chart to identify the cause; the CPU is still executing the program.