Overview: Why SET and S Are Not the Same Instruction
In Siemens STEP 7 (SIMATIC Manager, Step 7 V5.x) and the newer TIA Portal, the SET instruction and the S (Set bit) instruction are routinely confused by new users, particularly when working with Data Block (DB) bits referenced as DBx.DBX y.z. The confusion comes from the English word "set": both instructions appear to "set" something, but they act on entirely different targets.
- SET does not write to memory. It unconditionally forces the Result of Logic Operation (RLO) to signal state "1" for the remainder of the current network. It is a RLO control instruction, not a memory instruction.
-
S <bit> is a bit memory instruction. When the RLO at the moment of execution is "1", the addressed bit is latched to "1" and remains "1" until a
Rinstruction or a power-cycle/initial-start resets it.
If you assign the output of a SET to a DB bit using =, you create a write-once-per-cycle forced assignment, not a latched bit. If you use S, you create a true bistable (latching) element. Choosing the wrong one produces symptoms such as "the bit never stays on," "the bit is always on," or "stop does not work." This reference clarifies the difference and provides working start/stop logic on a DB bit for S7-300/400, with cross-platform notes for S7-1200/1500 in TIA Portal.
Prerequisites
Before implementing the examples in this article, confirm the following:
- Hardware: Any S7-300, S7-400, ET 200S (with IM 151), or a PLCSIM instance. For TIA Portal cross-checks, an S7-1200 (CPU 121x/1215/1217) or S7-1500 (CPU 151x) is required.
- Software (classic): STEP 7 V5.7 (or V5.5/V5.6) with S7-PLCSIM and the S7-300/400 block library installed.
- Software (TIA): TIA Portal V17 or later with the corresponding CPU HSP.
-
Project structure: A
S7 Programcontainer with a configured hardware station (rack, power supply, CPU, and at least one DI16/DO16 signal module) and aDB2(or any user DB) defined as a global, non-optimized DB in classic STEP 7, or as a standard (non-optimized) DB in TIA Portal if you intend to address bits absolutely. -
Symbols: Symbolic names assigned to
I0.0("start"),I0.1("stop"), andQ4.0("A_green") in the symbol table for the classic example.
DB2.DBX 2.0 to compile, the DB must be unoptimized, or the bit must be declared with a fixed address in the data block declaration. See the TIA Portal cross-platform section below.Instruction Reference: SET, S, R, =, CLR
The following table summarizes the bit-level instructions relevant to the SET vs S question in STEP 7 STL. All instructions are valid in the S7-300/400 instruction set and in TIA Portal STL. The operand column lists the supported memory areas; bit means a single-bit operand.
| Instruction | Type | Effect on RLO | Effect on Operand | Valid Operands |
|---|---|---|---|---|
SET |
RLO control | Forces RLO = 1 | None directly; combined with = writes "1" to a target |
n/a (no operand) |
CLR |
RLO control | Forces RLO = 0 | None directly; combined with = writes "0" to a target |
n/a (no operand) |
S <bit> |
Bit memory | Reads RLO; if RLO=1 sets the bit, else no-op | Latches bit to "1" until R is executed with RLO=1 |
I, Q, M, L, DBX |
R <bit> |
Bit memory | Reads RLO; if RLO=1 resets the bit, else no-op | Latches bit to "0"; clears BR bit if bit = BR |
I, Q, M, L, DBX |
= <bit> |
Assignment | Consumes RLO | Writes current RLO (1 or 0) to the bit every cycle | I (output image), Q, M, L, DBX |
FP <bit> |
Edge detect | Detects 0->1 on RLO | Sets edge memory bit for one cycle | M, DBX (must be a non-temporary bit) |
FN <bit> |
Edge detect | Detects 1->0 on RLO | Sets edge memory bit for one cycle | M, DBX (must be a non-temporary bit) |
DB Addressing Syntax and Operand Structure
A Data Block bit in STEP 7 is referenced with the syntax DB<number>.DBX <byte>.<bit>. The example bit DB2.DBX 2.0 means:
-
DB2— Data Block number 2 (the instance or global DB opened by the call; for absolute addressing the CPU must have DB2 in the working DB or useOPN DB2first). -
DBX— Data Block bit access (one bit). -
2.0— Byte 2, bit 0 (byte/bit notation, not byte.offset).
For a non-bit, you would use DBB (byte), DBW (word, 2 bytes), or DBD (double word, 4 bytes). Example: DB2.DBW 4 reads byte 4-5 as a 16-bit word, and DB2.DBD 6 reads bytes 6-9 as a 32-bit double word.
To use a fully qualified DB reference without opening it first, prefix with the DB number, e.g. DB2.DBX 2.0 is fully qualified and the CPU automatically handles the DB register. For word/dword access on a DB that has not been opened, the syntax is the same and the CPU handles the load/store. If the DB has been opened with OPN DB2 previously in the same block, the bare DBX 2.0 also works, but the fully qualified form is preferred for clarity.
Step-by-Step: Implementing Start/Stop Latching on a DB Bit
-
Create the DB. In the S7 Program / Blocks folder, right-click and choose Insert New Object > Data Block. Name it
DB2. In the Properties, set the type to Shared DB and confirm that Standard block access is selected (not Optimized in TIA). Add a Boolean tag at addressDBX 2.0and name itlatched_run. - Create or open OB1. This is the cyclic main program where the latching logic runs each scan.
- Insert the network. Switch the editor to STL (View > STL) for the most direct mapping of the SET vs S question.
-
Write the start/stop network using
SandRon the DB bit:NETWORK 1 // Start/Stop latching on a DB bit A "start" // I0.0 (NO pushbutton) S DB2.DBX 2.0 // Set DB bit; latches if "start"=1 AN "stop" // I0.1 (NC pushbutton) — examined as 0 = press R DB2.DBX 2.0 // Reset DB bit when "stop" pressed A DB2.DBX 2.0 // Read current state of the DB bit = "A_green" // Q4.0 — process output - Save and download the hardware, the DB, and OB1 to the CPU.
-
Verify in online mode by toggling
I0.0andI0.1in the VAT or PLCSIM and observing the DB bit andQ4.0.
S and R are conditional on the RLO at the moment of execution, only the network branch that sees RLO=1 latches or resets the bit. The other branch is a no-op. This is the difference from SET + =, which would write "1" every cycle regardless of the input condition.Code Examples in STL, LAD, and FBD
Example 1 — Correct start/stop with S/R on a DB bit (STL)
NETWORK 1
A "start"
S DB2.DBX 2.0
AN "stop"
R DB2.DBX 2.0
NETWORK 2
A DB2.DBX 2.0
= "A_green"Example 2 — Demonstrating the SET instruction (STL)
NETWORK 3
A M 10.1
SET // RLO is forced to 1, regardless of M10.1
= DB2.DBX 2.0 // DB2.DBX 2.0 = 1 every cycle, NOT latched by S
CLR // RLO forced to 0
= DB2.DBX 4.0 // Always 0; shows the complement patternThis second example shows that SET does not latch. If OB1 execution stops or the bit is not re-assigned, the bit will hold its last written value in the DB but is not protected from being overwritten by another network that targets the same byte.
Example 3 — Equivalent Ladder (LAD) form
| "start" DB2.DBX 2.0 "A_green" DB2.DBX 2.0
|--| |----------------(S)DB2.DBX2.0----| | |--( )----| |--( )----
| | | | | | |
| DB2.DBX 2.0 | | "stop" | | | |
|--|/| "stop" -------(R)DB2.DBX2.0--| | ------|/ |----| | |
| | | | |
| +-------------+ | |
| | | |
| +--|"start"|-----+ |
| |
| +-- (S)In LAD, the S and R contacts on a DB bit are configured through the bit operand pull-down; the editor writes the same DB2.DBX 2.0 internally.
Example 4 — Equivalent Function Block Diagram (FBD) form
"start" --->|----+--S-- DB2.DBX 2.0
|
"stop" --->|----+--R-- DB2.DBX 2.0
DB2.DBX 2.0 --->|----+-- = -- "A_green"Example 5 — SCL form for TIA Portal / S7-1200/1500
IF "start" THEN
"dbLatch".run := TRUE; // Equivalent to S DBx.DBX y.z
END_IF;
IF NOT "stop" THEN
"dbLatch".run := FALSE; // Equivalent to R DBx.DBX y.z
END_IF;
"A_green" := "dbLatch".run;In SCL, an assignment with := behaves like = in STL (non-latching, every cycle), so the start/stop conditions are evaluated unconditionally each scan — which is the correct way to model a latching bit in SCL.
Comparison: SET vs S vs R vs = Assignment
| Property | SET | S <bit> | R <bit> | = <bit> |
|---|---|---|---|---|
| Class | RLO control | Bit memory | Bit memory | Assignment |
| Modifies operand directly | No (must be paired with =) | Yes (latches) | Yes (latches) | Yes (writes RLO) |
| Persistent across scans | No — must be re-driven each cycle | Yes, until R or restart | Yes, until S or restart | No — recomputed each cycle |
| Depends on RLO | No (overrides it) | Yes (only acts if RLO=1) | Yes (only acts if RLO=1) | Yes (writes the RLO value) |
| Use case | Force a network's RLO; default-true branches | Latch on rising condition (start, fault, request) | Unlatch on condition (stop, reset, acknowledge) | Mirror a computed state to a bit |
| Typical bug when misused | Cannot be used to retain a value alone | Bit cannot be cleared by an overlapping network that also assigns to it | Same as S, in reverse | Bit oscillates if input is chattery |
Common Pitfalls and Diagnostic Entries
SET as if it were a latched assignment. Code such as SET ; = DB2.DBX 2.0 writes a 1 every cycle; it does not latch. If the network is skipped (MCR, jump), the bit will reflect whatever other network wrote to it last.DB2.DBX 2.0 — one with S, another with = — the = network (executed last in the cycle) overwrites the latched bit each scan. Always keep latches and non-latched assignments in separate bytes, or guard the assignment with the latch's read-back.AN "stop" the reset executes when the stop input is 0 (an NC wired input). For a NO stop button, use A "stop" in a separate network and apply the appropriate edge/interlock. The original example used an NC stop; this is the safer industrial convention.DB2.DBX 2.0 against an optimized DB, TIA Portal raises the compile error "Bit address DB2.DBX 2.0 not declared" or the bit is silently remapped. Switch the DB to Standard (non-optimized) access or use a tag name like "dbLatch".run.Verification and Online Monitoring
After downloading, verify the latching behavior with these steps:
- Open the VAT or a watch table and force
I0.0= 1,I0.1= 1 (NC, not pressed). ConfirmDB2.DBX 2.0= 1 andQ4.0= 1. - Force
I0.0= 0. ConfirmDB2.DBX 2.0remains 1 (latch holds) andQ4.0remains 1. - Force
I0.1= 0. ConfirmDB2.DBX 2.0resets to 0 andQ4.0drops to 0. - Toggle
I0.0andI0.1in the reverse order to confirm priority: ifSandRare both RLO=1 in the same cycle, the last one executed in the network wins. Reorder the branches if reset-priority is required (typical for safety). - Use Monitor/Modify on the DB to confirm the tag
dbLatch.runreflects the bit value byte-for-byte.
For deterministic testing, add a 1-second pulse generator on M10.0 and wire it to a counter that increments on each set of DB2.DBX 2.0. Confirm the counter increments exactly once per push of I0.0, not on every cycle.
Cross-Platform Notes: TIA Portal and S7-1200/1500
The SET/S/R/= instruction set is identical between STEP 7 V5.x and TIA Portal in STL. Where the two platforms differ is in the default DB access mode and the recommended way to address bits:
-
Default DB access. TIA Portal creates new DBs as optimized by default. Optimized DBs do not expose byte offsets to user logic; bit tags are accessible by symbolic name only. For
DB2.DBX 2.0style access, set the DB access to Standard in the DB Properties > Attributes tab. -
Symbolic access in SCL. On S7-1200/1500, SCL is the typical language for DB logic. Use
"dbLatch".run := TRUE;rather thanS. The compiler emits a latching pattern for FB instance DBs and a single-cycle assignment for shared DB tags. - Retain attribute. If you need the latched DB bit to survive a power cycle, declare the tag as RETAIN in the DB. Without RETAIN, OB100 startup initialization may set the bit back to its initial value (default 0) on warm restart.
-
OPC UA exposure. Symbolic DB tags are visible by default in the OPC UA server of the S7-1500 CPU. Absolute
DBXaddressing is not; use symbolic names if you intend to expose the bit to a SCADA. -
S7-200/S7-200 Smart exception. STEP 7 Micro/WIN uses V memory, not DBs. The
SandRinstructions exist with the same semantics; the equivalent write toVmemory isS V1000.0/R V1000.0.
Troubleshooting Matrix
| Symptom | Likely Cause | Diagnostic | Remedy |
|---|---|---|---|
| DB bit never goes high, even when input is true | DB not downloaded; wrong DB number; DB optimized (TIA) | Online > Accessible Nodes > show loaded blocks; check DB number in VAT | Download DB; correct the DB number; switch DB to non-optimized access |
| DB bit is always high, regardless of inputs | Unconditional SET ; = pattern; overlapping = overwriting a latch |
Cross-reference the DBX byte; check all write sites | Replace SET ; = with a conditional S/R; isolate the latch in its own byte |
| DB bit sets, but stop does not clear it | Stop branch is NO instead of NC, or polarity is reversed | Force I0.1 in VAT; observe the R branch RLO | Use AN "stop" for NC; add edge logic if bounce is suspected |
| DB bit flickers at scan rate | Both S and R active in same cycle (chatter) |
Online monitor with cycle time stamp | Add input debounce in HW config or in the OB |
| Compile error: "Bit address not declared" | Optimized DB; bit offset not used; pointer without AT | DB properties > Attributes > access mode | Switch to Standard access or declare AT view in SCL |
| DB bit resets on warm restart unexpectedly | Tag lacks RETAIN attribute | DB declaration review | Set RETAIN = true on the tag |
| SF LED on CPU; diagnostic buffer "Area length error" | Address outside DB length | PLC > Diagnostics Buffer | Correct byte/bit offset; recompile and download |
| Variable table shows DBX=0, but Q output is on | Output is driven by a different network; = mirroring another bit |
Cross-reference Q4.0 | Remove duplicate drive; use a single source of truth |
Frequently Asked Questions
What is the difference between the SET instruction and the S bit instruction in STEP 7?
SET is a RLO control instruction that forces the result of logic operation to "1" for the rest of the network; it does not write to memory on its own. S <bit> is a bit memory instruction that latches the addressed bit (for example DB2.DBX 2.0) to "1" whenever the RLO is "1" and holds that value until a R instruction runs with RLO=1.
Can I use SET to latch a bit in a Siemens Data Block?
No. SET only modifies the RLO. To latch, pair it with = <bit> in a network that runs every cycle, but that is non-latching and overwrites the bit on every scan. The correct latching instructions are S and R, or, in SCL, a conditional := TRUE / := FALSE pattern that is re-evaluated each cycle.
What happens if S and R are both active in the same cycle on the same DBX bit?
The last instruction executed in the network wins. If S is evaluated first and R second, the bit is reset; reverse the order to make S dominate. For safety-critical reset-priority logic, place the R branch after the S branch and consider adding a dedicated safety FB.
Why does DB2.DBX 2.0 give a compile error in TIA Portal?
The DB is optimized by default, which hides the byte/bit offsets from user logic. Open the DB's Properties and switch the access mode to Standard (non-optimized), or use a symbolic tag such as "dbLatch".run in SCL/LAD/FBD instead of an absolute address.
How do I make a DB latched bit survive a CPU restart?
Declare the tag in the DB with the RETAIN attribute set to true. On a warm restart, OB100 (or the CPU's startup OB) will leave retained tags at their last value, so the latched state persists. Without RETAIN, the tag is re-initialized to its start value (default FALSE) on every restart.