Troubleshooting S7-1200 CPU 1215C HSC Frequency Measurement

Problem Statement

A Siemens SIMATIC S7-1200 CPU 1215C DC/DC/Rly with order number 6ES7215-1HG31-0XB0 and firmware V3.0.1 is configured for high-speed counter (HSC) frequency measurement. A 20 V DC calibrator is used as a frequency source, programmable at 10 Hz, 25 Hz, and 100 Hz, and is applied to multiple digital inputs. When the calibrator drives the input, the HSC does not register counts. The same inputs respond correctly to a manual pushbutton, which implies the DI module and the CPU itself are partially functional but the HSC path is not being excited by the calibrator signal.

This symptom pattern — pushbutton works, frequency source does not — almost always points to a reference-voltage (0 V common) or signal-amplitude issue at the DI terminals rather than an HSC configuration defect. The discussion converges on the missing 0 V common between the calibrator and the CPU 1M terminal. This article expands that hypothesis into a complete field procedure: confirm wiring, then confirm TIA Portal HSC configuration, then confirm runtime enablement, then verify with an oscilloscope and a known frequency source.

Root Cause Analysis

Three failure classes can produce the observed behavior on an S7-1200 HSC input. Diagnose them in order of probability before changing the project.

Sources for further detail on the S7-1200 HSC hardware model and the 0 V common requirement: SIMATIC S7-1200 Programmable Controller System Manual, section on wiring the digital inputs.

Hardware Context: CPU 1215C 215-1HG31-0XB0 and HSC Terminal Map

The CPU 1215C DC/DC/Rly 6ES7215-1HG31-0XB0 carries the following integral I/O on the firmware V3.0.1 image:

For DC inputs, the type 1 thresholds are defined in IEC 61131-2: a voltage at or below 5 V is interpreted as logic 0, a voltage at or above 15 V is interpreted as logic 1. The CPU 1215C DC inputs source current from the field device into the input (PNP / sourcing convention) when 1M is at 0 V. The input draws approximately 4 mA nominal at 24 V.

Each HSC on the CPU 1215C is permanently bound to a specific set of digital inputs. The first three are the A/B/Z (clock/direction/synchronization) inputs; HSC5 and HSC6 use a subset.

For frequency measurement on a single-ended source, only the clock A input is required. The B and Z inputs can be left disconnected or assigned to other functions. The 1M terminal is the 0 V reference for I0.0 through I0.7, which is the group that includes the HSC1, HSC2, and HSC3 clock inputs.

Hardware reference: SIMATIC S7-1200 System Manual, chapters on CPU 1215C and on digital input wiring.

Wiring Verification: The 1M Common Connection

The 1M terminal on the CPU 1215C is not a power supply. It is the low-side reference for the digital inputs in its group. If a sourcing (PNP) field device is used, the device 0 V output must be tied to 1M, or to a 0 V bus that is bonded to 1M. If 1M is left floating, the input has no defined low reference and the apparent input voltage is undefined — typically the input floats near 0 V and never reaches the 15 V 1 threshold.

Procedure to verify the 0 V common is correct:

1. Power the CPU and the calibrator from the same 24 V supply (preferred) or bond their 0 V rails together with a short, dedicated wire.
2. With a digital multimeter in DC volts mode, measure between the calibrator LO (−) terminal and the CPU 1M terminal. The reading must be at or below 0.5 V DC. If it floats to several volts or reads 24 V, the common is missing or reversed.
3. Measure between the calibrator HI (+) terminal and the CPU 1M terminal while the calibrator is set to 20 V DC steady. The reading must be at or above 19 V DC under load. If it droops below 15 V, the calibrator cannot source the 4 mA required by the DI.
4. If the wiring is correct, switch the calibrator to 100 Hz and observe the DI status LED on the CPU. The LED for I0.0 (or whichever DI is wired) must flicker at 100 Hz. If it does, the HSC path is open and the defect is downstream in the TIA Portal configuration.

Signal Threshold and Filter Behavior at 20 V

The 20 V DC level is inside the 1 range for type 1 inputs (15 to 30 V). There is no need to boost the calibrator output to 24 V to make the input work. However, three subtleties matter:

1. Current sourcing. The DI nominal input current at 24 V is 4 mA. At 20 V the input current drops to roughly 3.3 mA, which is still inside spec. A calibrator with a current limit of 1 mA or less will not be able to develop the full 20 V at the input; the voltage will collapse toward the calibrator compliance limit. Verify with a scope under load.
2. Input filter. TIA Portal allows the input filter on each DI to be set from 0.1 µs to 12.8 ms. The default 6.4 ms setting rejects 100 Hz cleanly (6.4 ms equals one half-cycle of 78 Hz), but the filter is implemented as a debounce on the standard input, not on the HSC clock. The HSC clock path uses a separate, much faster filter, configurable under the HSC properties (typically 0.1 µs to 12.8 µs). For 10–100 Hz sources, the filter is irrelevant; the time-base for the HSC is the firmware hardware divider, not the DI filter.
3. Sensor / encoder type. Under the HSC properties, the encoder type can be set to 24 V PNP (sourcing) or 24 V NPN (sinking), depending on TIA Portal version. For a sourcing 20 V calibrator, the encoder type must be PNP. If the project is set to NPN, the HSC expects a sinking field device and will not count on a PNP source.

TIA Portal HSC Configuration for Frequency Mode

Open the device configuration of the CPU 1215C, navigate to Properties → High-speed counter (HSC) → HSC1, and set the following fields. The exact wording depends on the TIA Portal version; for V3.0.1 firmware the relevant TIA Portal release is V13 (or V13 SP1 for newer projects).

Compile the project and download the hardware configuration to the CPU. The HSC will not function on the bench even with the correct wiring until the configuration is loaded. If you are using a signal board (SB) or signal module (SM) for additional DIs, the HSC must be assigned to the onboard DI terminals; HSC functions on SB/SM DIs have separate, restricted assignments that vary by module.

Reference: S7-1200 System Manual, section on HSC configuration and wiring.

User Program: CTRL_HSC and Frequency Readout

The HSC requires runtime enablement in the user program. Configuration in TIA Portal brings the HSC online, but the run-time controls (enable, reset, change count value, change reference value) are driven from the program. For S7-1200, the runtime control is the CTRL_HSC instruction (or the High_Speed_Counter technology object, depending on the TIA Portal version).

The CTRL_HSC instruction is found in the Instructions task card under Extended instructions / High-speed counter. Drop it into a cyclic OB (typically OB1). It instantiates a background DB that holds the HSC hardware ID and runtime state.

Minimum required call to enable HSC1 and reset its count on demand:

// CTRL_HSC call
// HSC1, hardware ID from device configuration
"CTRL_HSC_1_DB"(HSC        := 1,        // HSC identifier (or hardware ID)
              CV         := 0,        // New count value on a reset
              RV         := 0,        // New reference value (compare value)
              PERIOD     := 1000,     // Evaluation window in ms for frequency
              DIR        := FALSE,    // Direction control; FALSE = count up
              NEW_DIR    := FALSE,    // Apply new DIR value
              NEW_CV     := FALSE,    // Apply new CV value on next 1 to 0 transition of REQ
              NEW_RV     := FALSE,    // Apply new RV value
              NEW_PERIOD := TRUE,     // Apply new PERIOD value
              EN         := TRUE,     // Enable the HSC at runtime
              REQ        := FALSE,    // Rising edge = apply pending NEW_* values
              BUSY       := ,         // In progress
              STATUS     := );        // Status word; 0 = no error

To read the measured frequency, use the process image tag of HSC1. By default the count value is at %ID1000 (DINT) for HSC1. For frequency measurement, the count increments in the configured evaluation window, and the firmware also publishes a measured value tag — in TIA Portal this is typically %ID1004 for HSC1, but the exact location is set in the HSC properties under I/O addresses. Verify the address in the device configuration for the project.

A simple SCL block to read the measured value and convert to engineering units (Hz, integer):

// Read HSC1 measured value, scale and clamp
#iRaw       := "HSC1_MeasuredValue";        // DINT, raw count in evaluation window
#iWindow_ms := "HSC1_Config".PERIOD;         // Evaluation window in ms
#rFrequency_Hz := INT_TO_REAL(#iRaw) * 1000.0 / INT_TO_REAL(#iWindow_ms);
IF #rFrequency_Hz > 32767.0 THEN
    #rFrequency_Hz := 32767.0;
END_IF;
#iFrequency_Hz := REAL_TO_INT(#rFrequency_Hz);

Reference: S7-1200 System Manual, section on CTRL_HSC and the HSC runtime interface.

Step-by-Step Diagnostic Procedure

Run this procedure in order. Stop at the first step that fails and apply the indicated fix.

1. Power and common. Verify the CPU and the calibrator share a 0 V bond. Measure between calibrator LO and CPU 1M; expect 0.5 V DC or less. If higher, add a bonding wire.
2. Signal at the terminal. With the calibrator at 20 V DC steady, measure between I0.0 and 1M. Expect 19 V DC or higher. If lower, the calibrator cannot drive 4 mA. Replace with a higher-current source or buffer the output with a driver stage.
3. DI LED check. Switch the calibrator to 100 Hz. The I0.0 LED on the CPU must visibly flicker. If it is solid on or solid off, the signal is DC, not pulsed — verify the calibrator output mode.
4. DI status in TIA Portal. Go online with the CPU, open the watch table, and force the I0.0 tag to monitor. At 100 Hz the tag must toggle at 100 Hz in the watch table. If it does not, the wiring or signal source is at fault.
5. Pushbutton test. Disconnect the calibrator. Wire a 24 V pushbutton between 24 V and I0.0, with 1M at 0 V. Manually press the button and watch the HSC count value in the watch table. If the count increments by 1 per closure, HSC1 is enabled and configured correctly. The defect is then on the calibrator side (steps 1–3).
6. HSC enable and operating mode. With the project online, open the device configuration and verify HSC1 is enabled, operating mode is Frequency, and the encoder type is PNP. If any of these is wrong, correct the configuration and download.
7. CTRL_HSC enable. In the user program, verify the EN input of CTRL_HSC is TRUE and the STATUS output is 0. A non-zero STATUS indicates a configuration or runtime error; look up the value in the S7-1200 System Manual.
8. Filter check. If the I0.0 LED flickers but the HSC count does not increment, the HSC input filter may be misconfigured. Set the HSC clock input filter to 0.1 µs in the device configuration and download.
9. Oscilloscope verification. If steps 1–8 pass and the HSC still does not count, place an oscilloscope probe on the I0.0 terminal. The waveform must show a 20 V peak square wave at the calibrator set frequency. A distorted, drooping, or noisy waveform indicates a source-side defect.
10. CPU firmware upgrade consideration. V3.0.1 is a legacy firmware version. If the project permits, consider a firmware update to the latest V4.x image. Always back up the project and verify hardware compatibility before upgrading.

Verification Tests and Acceptance Criteria

After applying a fix, run the following acceptance tests. Pass criteria are stated explicitly so the issue is not declared resolved prematurely.

Error Codes and Status Flags

The STATUS output of CTRL_HSC and the diagnostic buffer of the CPU report HSC faults. The codes below are the ones most often encountered in field service on the S7-1200.

Note: Hex codes other than 80A1–80D1 may appear with newer firmware or technology object variants. Always consult the S7-1200 System Manual for the specific firmware image and TIA Portal version in use.

Platform and Firmware Notes

CPU 1215C 6ES7215-1HG31-0XB0 ships in several firmware generations. The V3.0.1 image in the source post is from 2013–2014 and predates the technology-object approach for HSC that became standard in TIA Portal V14. Differences that affect a frequency-measurement project:

• V3.0 / V3.0.1 (TIA Portal V13). HSC is configured directly in the device properties. The runtime interface is the CTRL_HSC instruction with a background DB. The HSC tag addresses (count value, measured value) are visible in the device configuration under I/O addresses.
• V4.0 / V4.1 / V4.2 (TIA Portal V14 / V15). HSC is configured as a High_Speed_Counter technology object. The runtime interface is the technology DB; CTRL_HSC is still available but the technology object is the recommended path.
• V4.3 / V4.4 / V4.5 (TIA Portal V15.1 / V16 / V17). Additional HSC operating modes are exposed, including enhanced frequency and velocity measurement. The technology object API is stable across these versions.

Upgrade path considerations: the V3.0.1 project can be opened in TIA Portal V13 SP1 and updated in place. A direct jump to V4.x requires re-licensing the project in TIA Portal V15 or later and re-validating the HSC configuration. The hardware (215-1HG31-0XB0) is supported in all listed firmware versions; only the firmware image and the project need to change.

For projects that span CPU generations, use the cross-reference in the TIA Portal project tree to find every instance of CTRL_HSC and every HSC tag, and re-validate them after any firmware or TIA Portal upgrade. Also verify that the HSC count-value address (default ID1000 for HSC1) is not reused as a writable flag elsewhere; the count value is read-only from the user program and writing to it has no effect.

Frequently Asked Questions