Troubleshooting S7-1200 HSC Counting Errors with SICK DF60

Troubleshooting S7-1200 HSC Counting Errors with SICK DF60 Encoder

Field reference for engineers commissioning a SICK DF60 programmable incremental encoder on a Siemens SIMATIC S7-1200 CPU 1214C AC/DC/Relay (MLFB 6ES7214-1BG40-0XB0). Symptoms, signal-frequency budget, input-filter mathematics, root-cause analysis, wiring fix, and verification steps are documented below.

1. Problem Summary

The HSC input fails to register all encoder transitions, counting only a fraction of the expected pulses at 1400 RPM. A SICK DF60 (programmed to 360 PPR) wired to an S7-1200 HSC channel reports an apparent count rate of a few kHz rather than the calculated 8.4 kHz, 16.8 kHz, or 33.6 kHz expected for single, x2, or x4 quadrature evaluation. The symptom persists across multiple TIA Portal V13 HSC configurations and survives changes to the input filter.

2. System Configuration

The CPU 1214C AC/DC/Relay variant accepts 85–264 VAC on the line side and provides an internal 24 VDC sensor supply usable for low-current encoders. HSC-capable inputs are 24 VDC type and isolated from the relay outputs. The relay variant differs from DC/DC/DC and DC/DC/Relay only in line-side power; HSC performance on I0.0–I0.5 is identical at 100 kHz single-phase and 100 kHz quadrature (firmware V4.x).

3. Signal Frequency Budget

Calculate the expected HSC frequency before chasing firmware bugs. A 360 PPR encoder at 1400 RPM delivers:

f_base = (RPM / 60) × PPR = (1400 / 60) × 360 = 23.333 × 360 = 8 400 Hz

This is the base frequency of channel A (or B) alone. With HSC counting mode, the apparent input frequency to the counter is multiplied by the evaluation mode:

All three cases are well under the 100 kHz ceiling of the S7-1200 HSC. The input is therefore not exceeding HSC bandwidth; the symptom must originate in the filter, the wiring, the input threshold, or noise.

4. HSC Frequency Limits on CPU 1214C (6ES7214-1BG40-0XB0)

Per the SIMATIC S7-1200 System Manual, the onboard HSC inputs on I0.0 through I0.5 of the CPU 1214C (firmware V4.x) support:

• Maximum counter frequency: 100 kHz single-phase, 100 kHz quadrature (x1, x2, x4)
• Number of HSC channels: up to 6 (HSC1–HSC6)
• Counting modes: single (internal direction), two-pulse (CW/CCW), AB quadrature (x1, x2, x4)
• Counting range: −2 147 483 648 to +2 147 483 647 (DInt)
• Supported interrupts: CV = PV, CV = RV, direction change, reset, HSC ID

The HSC ceiling is not the constraint here. The pulse train never exceeds 33.6 kHz even at x4 mode. Engineers are advised to confirm this calculation on paper before changing HSC parameters.

5. Root Cause: Floating 24 V Common Reference

The encoder requires a 24 VDC supply and a return path. The PLC input compares each pulse against its own 24 V common terminal (1M for inputs I0.0–I1.5 on CPU 1214C). If the encoder is powered from a separate 24 VDC source whose 0 V terminal is not bonded to PLC 1M, the two references float independently and the differential signal seen by the PLC input collapses below the switching threshold on every other transition.

Symptoms of a floating common:

• Counter registers some pulses but skips others, especially at higher RPM.
• LED on the PLC input flickers dimly or does not illuminate at all, even though the encoder output LED indicates activity.
• Count rate scales with motor speed but consistently undercounts (e.g., 25 % or 50 % of expected).
• Touching the encoder cable shield or body of the encoder alters the count.
• Scope probe on the PLC input terminal shows the waveform riding on a slowly drifting common-mode voltage rather than referenced to PLC 1M.

Fix: Bond the encoder 0 V return to PLC terminal 1M (input common). If the encoder is powered from the PLC's onboard sensor supply ("L+" / "M"), this connection exists internally. If the encoder is powered from an external 24 VDC supply, a dedicated wire must connect the external supply 0 V to PLC 1M — there is no internal bond between independent 24 V sources.

6. Minimum Digital Input Filter Calculation

Each S7-1200 digital input applies a hardware + software debounce filter. The user-configurable filter must be less than half the smallest pulse width to ensure the input reliably sees the transition:

t_filter_max = T_pulse / 2 = 1 / (2 × f)

For the worst-case x4 mode (33.6 kHz):

t_filter_max = 1 / (2 × 33 600) = 14.9 µs

For x2 mode (16 776 Hz):

t_filter_max = 1 / (2 × 16 776) = 29.8 µs

The field note "1/16776 = 0.0005 s = 50 µs" mixes two calculations and is arithmetically inconsistent. The correct values are:

In TIA Portal V13, the input filter options for the onboard HSC-capable inputs are typically 0.1 ms, 0.2 ms, 0.4 ms, 0.8 ms, 1.6 ms, 3.2 ms, 6.4 ms, and 12.8 ms (and "none" on firmware V4.0 and later). At 100 µs the filter is below the half-period for 8.4 kHz (59.5 µs needed) but too high for x4 mode. Selecting "none" (firmware permitting) is recommended for HSC; if the filter cannot be disabled, choose the smallest available step. Selecting a larger filter value (e.g., 6.4 ms) will silently drop the counter to zero.

7. Correct Wiring for Encoder Supply Reference

The S7-1200 CPU 1214C AC/DC/Relay provides two relevant commons on the input side:

• 1M: 24 V common reference for inputs I0.0–I1.5 (and bonded internally to sensor supply "M")
• 2M: 24 V common reference for inputs on a higher-density signal board or signal module — not used here

Encoder wiring (SICK DF60, 360 PPR, NPN or PNP HTL):

1. Encoder VCC → PLC "L+" (sensor supply +24 V) OR external 24 VDC + terminal.
2. Encoder GND → PLC "M" / 1M (input common) — this is the wire that resolves the fault.
3. Encoder A → PLC I0.0 (HSC1 A).
4. Encoder B → PLC I0.1 (HSC1 B).
5. Encoder Z (index) → PLC I0.2 if used.
6. Encoder shield → PE at panel entry only (single-point ground); do not ground at both ends.

If the encoder is powered from a separate 24 VDC source (Phoenix Contact QUINT, Siemens SITOP, Beckhoff EL9580, etc.), run a dedicated 0 V return wire from the external supply negative terminal back to the S7-1200 1M terminal. The two negatives must be at the same potential. Use a wire gauge at least equal to the supply conductor (typically 0.75–1.5 mm²) and keep the run short.

8. TIA Portal V13 HSC Configuration Steps

1. In the project tree, open "Device configuration" for the CPU 1214C.
2. Select the CPU symbol and open "Properties" → "Digital inputs".
3. For each HSC-capable input (I0.0–I0.5), set the input filter to the lowest value available (typically 0.1 ms or "none" depending on firmware).
4. In the CPU properties, navigate to "High-speed counter (HSC)" and enable HSC1.
5. Select function type "Count" and counting mode "Quadrature x4" (or "x2" if pulse width is marginal due to long cable).
6. Assign input addresses: I0.0 = A, I0.1 = B, I0.2 = Z (optional index).
7. Set initial count value (typically 0), preset (PV), and reference value (RV) as required.
8. Enable CV = PV interrupt if a preset-triggered action is needed.
9. Compile and download to the CPU.
10. Use the online "Watch table" or "Force" view to read HSC1.CV live.

9. Verification Procedure

Use the following checklist to confirm HSC operation after wiring and configuration changes:

1. Drive the motor at a known speed, e.g., 1400 RPM commanded via the VFD.
2. Monitor HSC1.CV (current value) in the TIA Portal online watch table.
3. Compute observed frequency over a 1 s sample window:

   f_obs = (CV_now − CV_prev) / dt

   where dt is measured in seconds and the result is in Hz.
4. Compare to expected: 8 400 / 16 800 / 33 600 Hz depending on counting mode.
5. Tolerance: ± 1 % is acceptable; ± 5 % indicates filter or threshold issue; off by an integer factor indicates wrong counting mode or swapped A/B.
6. Toggle direction (CW vs. CCW) and verify the count increments vs. decrements correctly. If reversed, swap A and B at the PLC terminal — do not edit the HSC configuration.
7. Stop the motor; observe HSC1.CV should be stable. Drift indicates noise pickup.
8. Repeat the test at 10 %, 50 %, and 100 % of rated speed to verify linear response.

10. Field Commissioning Checklist

11. SICK DF60 Encoder Output Configuration Notes

The DF60 is programmed via the SICK SOPAS engineering tool over RS-232 or USB. For 360 PPR output on an HTL driver, the configuration parameters that affect HSC operation are:

• Pulses per revolution: 360 (configurable 1 to 65 536)
• Output level: HTL (24 V push-pull) recommended for S7-1200 inputs; TTL (5 V) requires a level shifter or signal board rated for 5 V.
• Output driver: Push-pull (preferred) vs. open-collector (requires pull-up resistor on PLC input).
• Direction inversion: Use to correct A/B lead-lag without rewiring.

If the DF60 is set to open-collector output and no pull-up is wired to 24 V, the high level will hover near 0 V and the PLC input will see only the encoder's internal pull-down (typically 4.7 kΩ) — too weak for reliable switching at high frequency. Confirm with a scope before assuming the encoder is at fault.

12. Troubleshooting Matrix

13. Related Configuration Notes

When expanding the system with a second encoder or a signal board (SB 1221), note that the HSC numbers HSC1–HSC6 are shared across the CPU and any plugged signal board. The signal board's digital inputs (typically I4.0–I4.3 on SB 1221) can serve as HSC inputs but are limited to 30 kHz single-phase / 20 kHz quadrature on the signal board — not 100 kHz. Always assign the high-speed channels to the CPU onboard inputs.

For multi-encoder systems requiring synchronized sampling, use the S7-1200's PTO/PWM outputs in tandem with HSC interrupts (CV = PV) rather than polling the CV in OB1. Polling at OB1 cycle time (typically 1–10 ms) misses fast transitions and introduces jitter.

FAQ