Troubleshooting Siemens S7 SR Flip-Flop: M10.0 Set/Reset Failure

Problem Overview

When programming an SR (Set-Reset) flip-flop in a Siemens S7 PLC using Statement List (STL), a common but subtle bug occurs when the same momentary bit (for example, M10.0) is wired into both the Set (S) and Reset (R) inputs of the flip-flop output coil. The rung appears syntactically correct, the controller accepts the download, the input contact closes when the push-button is pressed, yet the output never latches. The same logic works perfectly when the Set branch is driven by M10.0 and the Reset branch is driven by the actual output bit Q0.0.

This is a classic single-scan race condition caused by the cyclic execution model of the S7 CPU. It is not a hardware defect, not a wiring error, and not a firmware bug. It is a direct consequence of how the S7 scans the STL program and how the standard SR flip-flop instruction evaluates its inputs within a single OB1 cycle.

Root Cause: Single-Scan Set-and-Reset Collision

Consider this user-supplied network, written in classic S7-200 STL:

Network 1 (DOES NOT WORK)
A   M10.0     // Toggle command (e.g. push-button)
S   Q0.0      // Set output

A   M10.0     // Toggle command (same bit)
A   Q0.0      // Output state
R   Q0.0      // Reset output

Compare it with this network, which does work as a toggle:

Network 1 (WORKS)
A   M10.0     // Toggle command
A   Q0.0      // Output state
S   Q0.0      // Set output
R   M10.0     // Reset command bit

A   M10.0     // Toggle command
A   Q0.0      // Output state (true when output is ON)
R   Q0.0      // Reset output
R   M10.0     // Reset command bit

The two networks look almost identical. The single, critical difference is that the failing version evaluates M10.0 and Q0.0 simultaneously during the same scan, while the working version lets the Set branch latch Q0.0 before the Reset branch re-evaluates.

How the S7 CPU Executes the Failing Network

The S7-200, S7-300, and S7-400 CPUs all execute OB1 (the main cyclic program) top-to-bottom in a single scan. With M10.0 = 1 (push-button pressed) and Q0.0 = 0 at the start of the scan, the sequence of operations is:

1. Line 1: A M10.0 — RLO = 1
2. Line 2: S Q0.0 — Sets Q0.0 to 1 immediately in the process-image output (PIQ).
3. Line 3: A M10.0 — RLO = 1 (same bit, still TRUE this scan)
4. Line 4: A Q0.0 — RLO = 1 AND 1 = 1 (because step 2 just set it)
5. Line 5: R Q0.0 — Resets Q0.0 back to 0 within the same scan.

By the end of the scan, the Set and Reset have cancelled each other out. Q0.0 is left at 0, the LED never lights, and the operator assumes the instruction is broken. In reality, the flip-flop is working exactly as specified — it is the logic upstream of it that is feeding it contradictory commands during a single cycle.

Why the Working Version Works

In the working version, the first network places an extra R M10.0 instruction. This means:

• If M10.0 = 1 and Q0.0 = 0 at the start of the scan → Set branch fires, Q0.0 goes to 1, then M10.0 is forced to 0.
• When the second network is scanned on the same scan, M10.0 is already 0, so the Reset branch cannot fire.
• On the next push-button press, the cycle repeats, but this time Q0.0 = 1, so the Set branch is skipped and the Reset branch fires (because A M10.0 AND A Q0.0 are both 1). Q0.0 goes to 0.

The auxiliary R M10.0 is what breaks the single-scan race. Without it, the very bit that enables the Set is also the bit that enables the Reset within the same scan, guaranteeing a self-cancelling result.

Technical Background: Flip-Flop Theory

An SR flip-flop is a bistable element with two stable states. In its ideal form, the output Q is set to 1 by a Set pulse and held there indefinitely until a Reset pulse arrives. The truth table for the active-high SR latch is:

Reference: Flip-flop (electronics) – Wikipedia. The S7 SR instruction maps directly to this truth table, with Set dominant when both inputs are TRUE in the same scan.

Siemens SR Instruction Specifications

The standard Siemens SR flip-flop (FBD/LAD element, equivalent to two STL branches as shown above) has the following parameters:

Both STL S / R coil instructions and the FBD SR / RS blocks exhibit the same level-sensitive behavior. They are not edge-triggered; they sample their inputs on every OB1 pass. Reference: Siemens Industry Online Support – search the manual "SIMATIC S7-300/400 STL Programming" and the S7-200 System Manual for the canonical SR/RS element definitions.

Diagnostic Procedure

Use the following matrix to isolate the exact failure mode of a non-latching SR flip-flop in an S7 project:

Step-by-Step Verification

1. Open the affected FB/OB in STEP 7 or TIA Portal.
2. Place a VAT (Variable Table) online and add M10.0, Q0.0, and the input byte (e.g. IB0).
3. Toggle the push-button input. Watch the scan-by-scan state changes.
4. Confirm whether Q0.0 ever transitions to 1, or whether it pulses for one cycle and returns to 0.
5. Insert a breakpoint or single-scan step (S7-300/400 with breakpoint support) to see the precise scan order.

Solution 1: Use the Standard FBD/LAD SR or RS Block

For a true toggle function, the cleanest solution is the FBD RS (Reset-dominant) or SR (Set-dominant) block. In FBD the Set and Reset inputs are evaluated with deterministic priority — Set wins in the SR block. The equivalent STL pattern that achieves the same result is:

// Set-dominant toggle (recommended for one-push-button toggle)
A   M10.0        // Push-button (positive edge-detect via FP)
FP  M10.1        // Edge flag
S   Q0.0         // Set output

A   M10.0
AN  Q0.0
R   Q0.0         // Reset when button pressed and output already ON
R   M10.0        // Self-resetting command bit

Solution 2: Edge Detection with FP / Positive Edge

Use the FP (FlankenPositiv / positive edge) instruction to detect a true 0→1 transition. This guarantees the Set pulse lasts for exactly one OB1 scan, eliminating the possibility of a same-scan Reset collision:

// Edge-triggered SR toggle
A   M10.0
FP  M11.0        // M11.0 = edge memory bit
JCN NO_SET
S   Q0.0
JU  NO_RESET

NO_SET: A  M10.0
        A  Q0.0
        R  Q0.0
NO_RESET: NOP 0

The TIA Portal equivalent uses the |P| (positive edge) contact in LAD/FBD or P edge flag in STL. Reference: Siemens S7-1200/1500 System Manual, Section on Bit Logic Instructions.

Solution 3: Self-Resetting Auxiliary Bit (As Shown in the Working Version)

The simplest fix, which is what the user ultimately arrived at, is the R M10.0 line in the first network. By forcing the command bit back to 0 within the same scan that the Set was issued, you prevent the second network from seeing a TRUE Reset input during the same OB1 pass. The pattern is:

// Set branch
A   M10.0
AN  Q0.0
S   Q0.0
R   M10.0        // Forces M10.0 = 0 for the rest of this scan

// Reset branch
A   M10.0
A   Q0.0
R   Q0.0
R   M10.0

This is the canonical S7-200 toggle pattern, documented in the S7-200 System Manual. It is robust, uses no extra flags beyond the input image, and survives PLC restart because the output is initialized to 0.

Solution 4: Use the Dedicated RS Reset-Dominant Block

If you need guaranteed Set priority (for safety or process reasons), use the FBD RS block, which is functionally identical to the STL S / R pattern but with explicit Set-dominant semantics:

// FBD equivalent (paste into FUP/FBD editor)
RS(
   S   := M10.0,   // Set input
   R1  := M10.0 AND Q0.0,  // Reset only when button held AND output ON
   Q   := Q0.0
);

Common Edge Cases and Field Notes

1. Push-Button Debounce

If the physical push-button is bouncy, the Set and Reset branches may fire multiple times within a single mechanical press, producing erratic toggle behavior. Add an input debounce (OB1 cycle of 10–50 ms is usually enough) or use a hardware debounce filter on the digital input module. For S7-1200/1500, configure the input filter time in the device configuration. Reference: Siemens S7-1200 System Manual, Chapter 5 – Input Filter Configuration.

2. Retentive vs Non-Retentive Outputs

If the output Q0.0 is configured as retentive, the toggle state survives a CPU STOP→RUN transition. This can mask the race-condition bug because the operator may assume the toggle worked when in fact the previous latched state was retained. Use a non-retentive bit for the toggle target if you want each power-cycle to start with the output OFF.

3. Process Image Update Timing

On the S7-300/400, the process-image output (PIQ) is written to the physical outputs only at the end of OB1, not after every instruction. This means intermediate Set/Reset operations within OB1 do not affect physical outputs until the cycle completes. This actually helps mask the issue in some configurations but does not change the logical state of Q0.0 as seen by subsequent instructions in the same scan.

4. Cross-Network Order in FBD/LAD

When using FBD/LAD, the networks are scanned top-to-bottom in the same order as the user wrote them. The same Set/Reset race condition can occur across multiple networks, not just within a single one. The fix (R M10.0) must be placed in the first network that sets the output.

5. S7-1200/1500 Optimized Block Access

On S7-1200 (firmware V4.0+) and S7-1500 with optimized block access, the M10.0 and Q0.0 tags are no longer fixed to absolute addresses. The same logic applies, but use symbolic names ("ToggleButton", "LampOutput") for clarity. The race condition is identical and the fix is identical.

Verification Checklist

1. After applying the fix, power-cycle the CPU and confirm the output starts at 0.
2. Press the push-button once. The output should latch ON and stay ON after release.
3. Press the push-button again. The output should turn OFF and stay OFF.
4. Hold the push-button down. The output should toggle only once (edge-triggered behavior) or remain stable (level-triggered with priority) — confirm which behavior is expected by the process.
5. Run the program for 1,000+ cycles to verify no intermittent failures.
6. Disconnect the push-button and watch the output. It should hold its state indefinitely.

Summary of the Fix

The fundamental rule: never drive the Set and Reset inputs of an SR flip-flop with the same level-sensitive bit in the same scan unless you force that bit back to 0 within the same network. Use edge detection (FP / P), use a self-resetting auxiliary bit, or use the FBD SR / RS block with built-in priority. All three approaches are valid and supported in every S7 platform from the legacy S7-200 through the current S7-1500.