Using S7-1200 Analog Inputs as Digital Inputs: S7-1214C Guide

Overview

The Siemens SIMATIC S7-1214C DC/DC/DC (MLFB 6ES7214-1AG40-0XB0) ships with two on-board analog inputs (AI0 and AI1) and fourteen 24 V digital inputs. In many small machines and laboratory installations the digital I/O budget is exhausted long before the analog budget is. A common question in this situation is whether an analog input channel can be repurposed as an additional digital input, reading a clean 0 V / 24 V logic level as if it were a regular DI.

The short answer is yes, with a hardware interface. An analog input on the S7-1200 cannot tolerate the full 24 V of a sourcing output directly, but a two-resistor voltage divider reduces a 24 V digital signal to a value safely inside the 0 to 10 V measurement range. The scaled analog value is then compared against a fixed threshold in user program code to recreate an equivalent digital bit. This article covers the electrical design, the TIA Portal configuration, the threshold logic, the timing caveats, and the verification steps needed to deploy this technique on a real machine without damaging the analog front end.

S7-1214C Analog Input Hardware Characteristics

The two on-board analog inputs on the CPU 1214C DC/DC/DC are single-ended voltage or current inputs shared with a common return (M). The electrical limits that govern the analog-to-digital conversion are listed below. These values are taken from the S7-1200 Programmable Controller System Manual and apply to firmware V4.0 through V4.6 of the 6ES7214-1AG40-0XB0 CPU.

Several non-obvious constraints follow from this table. The 35 V DC absolute maximum means 24 V signals are inside the safe envelope, but a transient from a switched inductive load (solenoid, contactor coil) can easily exceed 35 V during turn-off. The on-board analog inputs have no TVS or RC protection of the kind found on the digital inputs, so a divider alone is not a complete interface - it must be paired with a free-wheeling path or a small Zener clamp if driven by an inductive source. The 100 kΩ input impedance is high enough that any divider with total series resistance below about 50 kΩ is loaded by less than 1 % and can be sized with a simple Thevenin calculation.

Reference: SIMATIC S7-1200 Programmable Controller System Manual, chapter on analog I/O.

Why Use an Analog Input as a Digital Input?

There are three realistic scenarios in which a machine builder deliberately turns an AI into a DI:

1. DI shortage with AI to spare. A small retrofit needs one or two additional 24 V inputs but there is no room for a SM 1221 DI module. Using a free AI avoids a hardware change order.
2. Voltage-proportional signals masquerading as digital. Some sensors emit a 0 to 10 V analog signal but the application only needs to know whether the signal is above or below a fixed threshold (e.g., a "part present" optical sensor with an analog output). Treating the AI as a 1-bit DI inside the program is often more robust than a full 0-10 V scaling block.
3. Diagnostic / debug capture. During commissioning, a technician wants to log the exact shape of a 24 V pulse train. Reading the AI on a slow scan captures the envelope and lets the PLC count edges using a software comparator.

Outside of these cases, the technique has no advantage and several disadvantages. It is slower, it consumes an analog channel that is typically more expensive per point, it requires scaling and threshold code, and it cannot replace a digital input in any safety chain.

Electrical Protection: Maximum Input Voltage and Damage Threshold

The S7-1200 on-board analog inputs are not designed for the 24 V nominal swing of the digital inputs. The published absolute maximum is 35 V DC continuous, but this is a survival rating, not an operating rating. Applying 24 V to a 0 to 10 V input will:

• Push the input past the top of the selected measurement range, clipping the ADC output at 27648 (for 0-10 V unipolar).
• Subject the input ESD / over-voltage clamp network to continuous stress, which can shorten the life of the part even if the chip does not fail immediately.
• Return an out-of-range flag (S7 analog "overflow" bit) that must be filtered in software, otherwise it will appear as a constant "ON" reading.

For these reasons a passive voltage divider is the recommended interface. A simple R1 / R2 pair drops the 24 V signal to a level safely inside the 0 to 10 V range while presenting a high enough source impedance that the input draws negligible current. The choice of 18 kΩ and 10 kΩ is field-proven and works because the total series resistance of 28 kΩ limits the divider current to about 0.86 mA at 24 V, which keeps resistor dissipation under 25 mW and is well above the noise floor of the analog input.

Voltage Divider Sizing for 24 V Digital Signals

Target the divider output so that a 24 V logic level produces a value comfortably inside the 0 to 10 V measurement range - typically 7 to 9 V. This gives noise margin at both ends (residual offset when the source is OFF, and headroom when it is ON).

With R1 = 18 kΩ (top, connected to the 24 V signal source) and R2 = 10 kΩ (bottom, connected to M):

V_AI = V_IN × R2 / (R1 + R2)
V_AI = 24 V × 10 / (18 + 10)
V_AI = 24 × 0.3571 = 8.57 V

Loaded by the analog input impedance (R_in ≥ 100 kΩ), the actual voltage at the AI pin is:

R_parallel = (R2 × R_in) / (R2 + R_in) = (10 × 100) / 110 = 9.09 kΩ
V_AI = 24 × 9.09 / (18 + 9.09) = 24 × 0.3355 = 8.05 V

That is well inside the 0-10 V range and well below the 10 V full-scale limit. With a 1 % resistor tolerance on R1 and R2, the worst-case output for 24 V input is 7.78 V to 8.32 V. Threshold can be set midway at 8.0 V with no risk of false triggering.

Use 1/4 W metal-film resistors with 1 % tolerance. Avoid carbon-film 5 % parts in this position; their voltage coefficient will shift the divider ratio by tens of millivolts. If the source is a mechanical contact (relay or limit switch), add a 100 nF X7R ceramic capacitor in parallel with R2 to suppress contact bounce - the resulting RC time constant is 1 ms, which is faster than the analog conversion but slow enough to attenuate mechanical bounce above 1 kHz.

TIA Portal Hardware Configuration

The on-board analog inputs of the CPU 1214C are configured in the device configuration of TIA Portal V16 or later. The following steps assume the project already contains the CPU 6ES7214-1AG40-0XB0 and that you are editing the analog input properties in the Device View.

1. Open Devices & Networks and double-click the CPU.
2. Switch to Device View. In the slot table on the left, locate AI - Properties > AI2/AO2 (this is the on-board analog section of the CPU).
3. For channel AI0, set:
   • Measurement type: Voltage
   • Voltage range: 0 to 10 V (do not select ±10 V; the divider produces a unipolar signal)
   • Smoothing: enabled, with 4 to 8 cycles (≈ 100 ms to 200 ms). Lower values increase noise on the threshold comparison; higher values slow the digital response unnecessarily.
   • Integration time: 60 Hz rejection (16.67 ms per conversion). Use 50 Hz rejection (20 ms) on 50 Hz mains systems to keep hum out of the AI.
4. Leave the diagnostics box unchecked unless you want overflow / wire-break alarms - those will be triggered every time the divider pulls the AI above the 10 V full-scale on a transient.
5. Confirm and compile. The default input word address for the on-board AI is IW64 (channel 0 = IW64, channel 1 = IW66). On the CPU 1214C, the address is fixed by the system and cannot be remapped; signal modules added later start at IW72.

Reference: S7-1200 Automation System Manual, edition 06/2023 and the TIA Portal online help under "Configuring analog inputs".

Threshold Detection Logic Implementation

With the AI reading a raw integer between 0 (0 V) and 27 648 (10 V), the 8.05 V divider output produces a value near 22 257. A comparator turns that back into a boolean. Three equivalent implementations are shown below; pick the one that matches the rest of your program style.

Ladder (LAD) - single comparator

      IW64           14000       M0.0
|---| >=I |---( )---|
     "AI0_raw"

Threshold of 14 000 corresponds to roughly 5.06 V, which is well below the divider "high" output of 8.05 V (22 257) and well above the residual low-level reading (typically 0 to 200). Adjust the constant if the application is exposed to more or less noise.

Ladder (LAD) - comparator with hysteresis

For signals that will be dithered near the threshold (slow-changing pressure switches, for example), add a Schmitt-trigger pair to prevent flapping:

      IW64          16000      "DI_from_AI0_set"
|---| >=I |---(S)---|

      IW64          12000      "DI_from_AI0_reset"
|---| < I |---(R)---|

Set threshold: raw >= 16 000 (≈ 5.79 V)
Reset threshold: raw < 12 000 (≈ 4.34 V)
Hysteresis band: ≈ 1.45 V, which is wider than the analog noise of the divider on a quiet panel.

Structured Text (SCL) - clean threshold with sanity check

// "AI0_raw" : INT (raw analog input, IW64)
// "DI_from_AI0" : BOOL (equivalent digital state)
// "AI0_fault" : BOOL (range or wire-break alarm)

IF "AI0_raw" >= 16000 THEN
    "DI_from_AI0" := TRUE;
ELSIF "AI0_raw" < 12000 THEN
    "DI_from_AI0" := FALSE;
END_IF;

// Latch a fault if the input goes to 0 V (wire broken) or
// overrange when divider is shorted.
IF ("AI0_raw" = 0) OR ("AI0_raw" > 27648) THEN
    "AI0_fault" := TRUE;
ELSE
    "AI0_fault" := FALSE;
END_IF;

Wrap the comparator in a function block (FB) with an instance DB if more than one AI is being used as a DI. The FB exposes the raw value, the boolean state, the threshold high/low, and a fault flag. This is the recommended pattern for code that will be reused or handed off to maintenance.

Timing, Filtering, and Scan Considerations

An analog input on the S7-1200 is fundamentally slower than a digital input. The end-to-end latency from a 24 V edge arriving at the screw terminal to the comparator in the user program updating has three components:

This means a high-frequency pulse train from a proximity switch cannot be read with this technique. The S7-1200 on-board digital inputs, by contrast, can capture edges below 1 ms depending on the configuration of the input filters (0.2 ms to 12.8 ms in the device configuration). Use AI-as-DI only for slow events: end-of-travel limits, door-closed contacts, mode-selector switches, and similar signals where a 75 ms propagation delay is acceptable.

The S7-1500 has high-speed counter inputs (HSI) on the CPU itself and on the TM Count modules, but its on-board analog inputs are similarly slow. The same voltage-divider technique is fully applicable to an S7-1500 CPU such as the 1511-1 PN, but the threshold addresses and the I/O address ranges are different (S7-1500 analog input addresses start at IW0 with no fixed offset, configurable in the device view).

Commissioning and Verification Procedure

After wiring the divider and configuring the AI, run through the following verification sequence before trusting the equivalent DI bit in the running program. Each step has a pass/fail criterion that can be checked from a TIA Portal watch table or from the HMI.

1. Verify the divider output with the source OFF. Force the 24 V source to 0 V (or open the contact). In a watch table, monitor AI0_raw at IW64. The reading must be in the range 0 to 200. Anything above 1 000 means a wiring error (R2 open, M not connected, divider reference floating).
2. Verify the divider output with the source ON. Apply 24 V to the divider input. The reading must be in the range 18 000 to 24 000. If the reading is negative, R1 and R2 are reversed. If the reading is 32 000 to 32 767, the AI is in overflow and the divider is not dropping the voltage (R1 shorted, R2 open, or 24 V reaching the pin directly).
3. Measure the actual pin voltage with a multimeter. Set the meter to V DC and measure between the AI pin and M on the terminal block. With the source ON, expect 7.8 V to 8.3 V. With the source OFF, expect < 50 mV. These bounds assume 1 % resistors and a 24 V source accurate to ±5 %.
4. Confirm threshold triggering. With the source toggling slowly, watch DI_from_AI0 in a watch table. It must transition within 100 ms of the 24 V edge, and it must not chatter when the source sits at exactly 24 V (use the hysteresis version of the logic for this test).
5. Run a 24-hour soak test. Leave the source in a fixed state and use the PLC's trace or the HMI trend to log AI0_raw over 24 hours. The reading should not drift by more than 200 counts (≈ 70 mV). A larger drift indicates a thermally unstable resistor (replace 5 % carbon-film parts) or a ground-loop induced offset.
6. Functional test of the application. Drive the actual machine through the same sequence it runs in production. Confirm that the equivalent DI bit produces the expected actuator response in every state.

Common Pitfalls and Field-Proven Caveats

1. Forgetting the wire-break alarm. An analog input is fundamentally "wire-break = 0 V = FALSE", which looks like a legitimate OFF state. A real digital input would flag a wire break as a fault. The SCL block above adds a "raw = 0 for N seconds" check that sets a fault flag in the HMI, which is the minimum acceptable practice for AI-as-DI on a safety-relevant signal.

2. Mixing 0-10 V and 4-20 mA wiring conventions. On the CPU 1214C, current mode uses the same pin and a 250 Ω external sense resistor to convert 4-20 mA to 1-5 V. If a current-mode SM 1231 is later added, the sense resistor on the on-board AI must be removed, otherwise the divider is loaded by 250 Ω and produces almost no output. Document the divider in the schematic so the next technician does not "clean up" the wiring.

3. Smoothing set too low. A smoothing value of 1 cycle is the equivalent of an unfiltered ADC. The comparator will chatter at the threshold. A starting value of 8 cycles (≈ 130 ms) is a good balance between speed and noise rejection for most on-machine signals.

4. 24 V applied to the AI during PLC power-down. If the field device is powered from a 24 VDC source that is independent of the PLC, the AI pin can be driven while the PLC is off. Some analog front ends survive this, but the ESD diodes of the S7-1200 are not rated for sustained reverse current. Add a 1 kΩ series resistor at the AI pin if the field wiring is long or subject to induced voltages.

5. Threshold set to mid-scale. A divider output of 8.05 V is a raw count of about 22 257. Setting the threshold at 13 824 (mid-scale of 0-10 V) is too low and gives no margin against the divider's residual low-level reading of 0 to 200. Use a threshold of 16 000 or higher (≈ 5.79 V), or, for clean sourcing outputs, threshold at 20 000 (≈ 7.23 V) for a 1.5 V noise margin.

6. Using AI-as-DI for HSC (high-speed counter) functions. The S7-1200 HSC function block can only bind to the digital input channels or to a high-speed counter module. It will not bind to the on-board AI. If a high-frequency pulse train needs to be counted, do not use this technique.

Alternatives When AI-to-DI Is Not Appropriate

If the constraints above rule out the AI-as-DI approach, the alternatives in order of preference are:

• Add a SM 1221 DI module (e.g., 6ES7221-1BF32-0XB0, 8 DI 24 V, or 6ES7221-1BH32-0XB0, 16 DI 24 V). The 16-point module costs less than the engineering time spent on the divider for a high-reliability application.
• Add a digital input board on a remote ET 200S / ET 200SP station if the PLC has reached its maximum local SM count (eight signal modules on the S7-1200, fewer in some configurations).
• Use a relay output of the existing field device if the device has a relay contact available - this is a real DI source for the PLC and avoids any analog-domain processing.
• Repurpose a free DO as a pulsed input with a parallel resistor to the AI. This works only with bidirectional input/output channels on certain compact CPUs and is not applicable to the 1214C on-board I/O.

The AI-as-DI technique is at its best in prototyping and small-panel retrofits. For production machines with longer uptime requirements, prefer a real DI module.

Frequently Asked Questions