Building 6-Hour Inactivity Timers on the Omron CQM1H PLC

Problem Definition

A common field requirement on the Omron CQM1H modular controller is a long-duration watchdog: energize a pneumatic pre-charge valve for ten seconds when the controller first powers up or when the machine has sat idle (no operator buttons pressed) for six hours. The output counteracts cylinder leak-down so a soft-start is achieved whenever a long-inactive axis is first commanded to move.

The catch is the CQM1H's native timer ceiling. The TIM instruction accepts a set value of 0000–9999 BCD with a 0.1 s resolution, so its maximum preset is 999.9 s (≈16.7 min). The 6 h (21,600 s) interval is twenty-one times that ceiling, which rules out a single timer. The classic fixes are: cascade 22 sequential timers, build a 1 s or 1 min clock-and-counter chain, or use a 1 min clock pulse driving a single CNT with a preset of 360.

This article lays out all three strategies, shows the complete rung map for the recommended counter approach, and includes a verification procedure you can run on the bench before commissioning. The CQM1H is a legacy family (production ended well before 2020); a final section shows how the same logic ports to a modern CJ/NJ controller without changing the application behaviour.

Prerequisites

• CPU: CQM1H-CPU11, -CPU21, -CPU31, -CPU41, -CPU51 or -CPU61 (any variant supports TIM, TIMH, TMHH and CNT).
• I/O: One output point (e.g., 100.00) wired to the pre-charge solenoid, and N digital input points assigned to operator push-buttons (Start, Stop, Jog, Reset, mode-select, etc.).
• Programming software: CX-Programmer 9.x or Sysmac Studio with CQM1H CPU device file; offline simulation optional but recommended.
• Reference manuals: CQM1H CPU Unit Operation Manual (Cat. No. W363) and CQM1H Programming Manual (Cat. No. W364), both available from the CQM1H product family page on the Omron Industrial Automation portal.
• Optional: A real-time clock module (CQM1H-RTC) if you later need scheduled-on-time logic, but the inactivity timer does not require it.

CQM1H Timer and Counter Capabilities

Knowing the instruction set up front prevents wasted scan time and prevents silently truncated set values when you paste logic from an NX/CJ project.

The SR area clock-pulse bits (also called "clock flags") are the other key resource. The CQM1H generates them in hardware, so they cost zero scan time:

Note: verify the exact bit map against the CQM1H CPU Unit Operation Manual for the specific lot of your CPU; some early CQM1H-CPU11/-CPU21 firmware revisions renumber the 0.2 s and 1 s flags. Treat the table above as the canonical modern mapping.

Strategy 1: Cascaded TIM Instructions

The most direct — and least elegant — solution. Cascade 22 timers, each preset to 999.9 s. Timer 1's done bit enables timer 2, timer 2's done bit enables timer 3, and so on. Timer 22's done bit starts the 10 s pre-charge. Total elapsed time = 22 × 999.9 s = 21,997.8 s, which is slightly over 6 h. Trim the last timer to 602.2 s to land at exactly 21,600 s if you need an exact 6 h boundary.

Rung 1:  LD    P_First_Cycle       ; first scan
        OR    T0001.done         ; self-latch the chain
        AND NOT T0022.done        ; stop after 6 h fired
        TIM   0001  #9999         ; 999.9 s

Rung 2:  LD    T0001.done
        TIM   0002  #9999

... (rungs 3..21) ...

Rung 22: LD    T0021.done
        TIM   0022  #9999

Rung 23: LD    T0022.done
        DIFU  W0.00               ; one-shot into pre-charge trigger

Drawbacks. 22 rungs and 22 timers consumed for one function. Any rung in the chain resetting (mode change, download, power cycle) starts the count over, and there is no way to detect or reset individual timers. Do not use this pattern on a controller near its memory ceiling; on a CQM1H-CPU11 with 3.2 K words, 22 timers plus the 10 s timer and supporting relays are still well within budget, but as soon as you add a second long-duration timer, you begin losing headroom for the rest of the machine.

Strategy 2: 1-Second Clock Plus Cascaded Counters

Use the 1 s clock pulse (SR 253.03) to advance a counter whose preset equals seconds, then count the minute counter's completion pulses. For 6 h = 21,600 s you cannot fit that into a single CNT (max 9,999), so cascade two counters: 60 s → 360 min.

Rung A:  LD    253.03              ; P_1s clock
        AND NOT W0.10              ; 
        LD    W0.10                ; any input active OR'd into W0.10
        CNT   0001  #60            ; C0001 counts 60 seconds = 1 min

Rung B:  LD    C0001.done
        AND NOT W0.10
        LD    W0.10
        CNT   0002  #360           ; C0002 counts 360 minutes = 6 h

Rung C:  LD    C0002.done
        DIFU  W0.00                ; one-shot trigger to pre-charge

Counter C0001 resets every time the operator touches any input (W0.10), so the inactivity interval is measured from the last input transition. Counter C0002 cannot reset until C0001 has finished a complete 1-min window, which is exactly what we want — a rolling six hours of true inactivity.

Drawback. 21,600 seconds is computed from a hardware 1 s flag, so scan-time jitter is irrelevant, but you still consume two counter numbers. If the CQM1H-CPU is a -CPU11/-CPU21 (128-counter limit), this is fine; on a -CPU51/-CPU61 you can scale to days by simply changing #360 to #1440 (24 h) or #10080 (one week).

Strategy 3: 1-Minute Clock Plus Single Counter (Recommended)

The 1-minute clock pulse at SR 254.00 already exists in the CQM1H. It is on for 30 s and off for 30 s, so a counter that runs only while the clock is high will miss half the pulses. The correct pattern is to AND the clock with a flip-flop, or more simply, count the rising edges of the clock. Because CNT increments on a 0→1 transition and is unaffected by the duty cycle as long as the input is true for at least one scan, this works perfectly.

Rung 1:  LD    254.00              ; P_1min clock
        AND NOT W0.10              ; no input active
        LD    W0.10                ; any input active
        CNT   0001  #360           ; C0001 = 360 minutes = 6 h

Rung 2:  LD    C0001.done
        DIFU  W0.00                ; one-shot trigger

Two rungs, one counter, one work bit. The preset 360 is a clean BCD constant and reads intuitively on a print-out. The 30 s ON / 30 s OFF clock means a single missed scan will not skip an increment, and the counter value can be cross-checked on the CX-Programmer watch window without simulation.

This is the pattern to use in production. The remainder of the article builds the complete pre-charge stage on top of this counter.

Startup Trigger via P_First_Cycle (SR 253.15)

The CQM1H sets SR 253.15 for exactly one scan after the controller enters RUN mode (or after a power-on that auto-restarts). Treat it as a one-shot rising edge — never as a steady bit, because it will be 0 on every scan after the first.

Rung 3:  LD    253.15              ; P_First_Cycle
        OR    W0.00                ; 6-h trigger latched here
        AND NOT T0001.done         ; disable re-trigger while 10 s is running
        OUT   TR0

The internal relay W0.00 is the one-shot pulse generated in Strategy 3 when C0001 reaches its preset. As long as the 10 s timer T0001 is timing (or has just completed), the AND-NOT prevents a second trigger if the operator presses no input for another six hours straight away. The TR0 output feeds the next stage.

10-Second Pre-Charge Output Stage

The pre-charge valve should be on for exactly 10 s every time it is triggered. Use a TIM with a 0.1 s resolution, preset #100 (= 10.0 s).

Rung 4:  LD    TR0                 ; combined startup / 6-h trigger
        TIM   0001  #100           ; 10.0 s pre-charge interval

Rung 5:  LD    T0001.done          ; timer running flag (or .a/.b/.f depending on ladder style)
        OUT   100.00              ; pre-charge valve solenoid

Rung 6:  LD    T0001.done          ; self-clear the latched trigger
        OR    253.15               ; also clear on first scan to start clean
        RES   W0.00

The solenoid contactor is wired to output 100.00; if you use a different output module, change the operand but keep the rest of the logic identical. The RES (RESET) instruction on W0.00 ensures the next 6-h trigger starts a fresh 10 s window rather than re-triggering immediately on a residual latch.

ORing All Operator Inputs

The "no input pressed" condition requires ORing every operator push-button into a single work bit. Use a separate work bit for the OR, not the same bit that you reset the counter with, so the logic is readable during commissioning.

Rung 7:  LD    0.00                ; Start button
        OR    0.01                ; Stop button
        OR    0.02                ; Jog forward
        OR    0.03                ; Jog reverse
        OR    0.04                ; Reset / mode select
        OR    0.05                ; Auto / Manual
        OR    0.06                ; E-stop reset (after safety relay OK)
        OUT   W0.10

If the machine has more than seven buttons, use a second OR row on W0.11 and OR them together, or compute the OR inside an SBN/RET subroutine for cleanliness. Do not include the E-stop NC contact — only the E-stop reset pushbutton, so a true E-stop will not continuously reset the inactivity timer (you want the timer to keep counting through a fault so the next power-up fires the pre-charge).

Complete Ladder Logic

The full program requires seven rungs and the following operand budget. The IR, SR and TC areas are written in absolute form so the logic is portable between CPU models.

; ============================================================
; 6-h inactivity + 10-s pre-charge on CQM1H
; Author: field reference / CX-Programmer mnemonic listing
; ============================================================

; Rung 1  - OR all operator inputs into W0.10
LD    0.00       ; START
OR    0.01       ; STOP
OR    0.02       ; JOG +
OR    0.03       ; JOG -
OR    0.04       ; MODE
OR    0.05       ; RESET / ACK
OUT   W0.10

; Rung 2  - 6-hour inactivity counter (Strategy 3)
LD    254.00     ; P_1min clock
AND NOT W0.10
LD    W0.10
CNT   0001       ; PV = 360 min
#360

; Rung 3  - 6-h one-shot trigger
LD    C0001
DIFU  W0.00

; Rung 4  - Combine first-cycle and 6-h trigger
LD    253.15     ; P_First_Cycle
OR    W0.00
AND NOT T0001
OUT   TR0

; Rung 5  - 10-second pre-charge timer
LD    TR0
TIM   0001       ; PV = 100 (10.0 s)
#100

; Rung 6  - Pre-charge output
LD    T0001
OUT   100.00

; Rung 7  - Reset 6-h one-shot after timer fires
LD    T0001
RES   W0.00
END

I/O and Memory Allocation Table

Verification and Commissioning Procedure

Validate the logic on the bench before connecting the pre-charge valve, then again at the machine. The procedure below uses CX-Programmer online functions.

1. Compile and download. In CX-Programmer, select PLC > Compile All, then PLC > Transfer > To PLC. Confirm the CPU enters RUN and SR 253.15 pulses for one scan in the Watch window.
2. Confirm the 10 s pre-charge on power-up. Observe 100.00 turn on within one scan of RUN and remain on for 10.0 s ± one scan. Use the Differential Monitor tool on SR 253.15 if the pulse is too short to see in the regular monitor.
3. Confirm counter reset behaviour. Force C0001 PV to #359 via Set/Reset Forced Status. Press and release any operator button; the PV must drop to #000. Without an input press, the PV must advance by 1 every 30 s of the 1-min clock ON half (so PV = 1 at 30 s, PV = 2 at 90 s, etc., until PV = 360 at 360 × 60 / 2 = 10,800 s ≈ 3 h. Re-check this on your CPU: the P_1min duty cycle is documented as 30 s on / 30 s off in the CQM1H manual, but some revisions pulse only for one scan per minute. Use the on-line trend graph to capture the actual pulse width before relying on the count rate).
4. Confirm 6 h trigger. Shorten the test by temporarily changing the preset to #3, downloading, and waiting. The output must fire for 10 s at PV = 3, and the counter must reset to 0 when the timer completes (via Rung 7). Restore the preset to #360 after the test.
5. Confirm self-inhibition. Repeat step 4 with the preset at #3 and confirm that pressing no input for a second three-minute window does not re-trigger the pre-charge for one full scan after the first 10 s window closes. This validates the AND-NOT T0001 interlock.
6. Confirm the E-stop path. With the machine in Auto, force 100.00 ON via the Watch window and actuate the E-stop. The solenoid must drop out within the safety-rated response time. The timer logic must not latch 100.00 in a way that defeats the E-stop.
7. Document the final preset in the program comment and on the schematic, e.g. ; C0001 PV = 360 = 6 h inactivity window, 10 s pre-charge on overflow.

Troubleshooting Matrix

Migration to Modern Omron Controllers

The CQM1H family has been superseded by the CJ2 and the NX/NJ machine controllers. The same logic ports directly, but the operand names change. On a CJ2M-CPU3x with CX-Programmer 9.x:

• SR 253.15 is still P_First_Cycle (now A200.15 on the CJ2 area-A allocation; verify against the CS/CJ/NSJ Reference Manual Cat. No. W394).
• SR 254.00 is still the 1-minute clock; on a CJ2 it lives at A200.00 with a 1-minute cycle.
• The CNT instruction is unchanged; the preset is BCD, range 0–9999, so the Strategy 3 implementation is byte-for-byte identical.
• The DIFU and RES instructions also work on CJ2 with no syntax change.
• On an NJ/NJ controller running Sysmac Studio, the equivalent is a Ton timer with a 21,600,000 ms preset driving a Count instruction, or simply a TimeStamp subtraction: (currentTime - lastInputTime) >= PT#6h. Either approach uses structured text and benefits from automatic reusability across machines.

If you are migrating a working CQM1H program, copy the seven rungs verbatim, remap 0.00–0.05 to the new input addresses, remap 100.00 to the new pre-charge output, and verify the SR-to-A remapping using the CJ2 Operand Reference. No changes to the timer or counter logic are required.

FAQ