CLICK PLC Selection Logic Needs One Writer per State

A CLICK PLC and C-More Micro can implement an exclusive off/low/medium/high selector and HMI-adjustable step times, but make the PLC the sole owner of the final state and confirm how the installed CLICK program resolves conflicting SET and RST writes. Do not assume that two instructions acting on one bit leave it reset: the reported CLICK behavior conflicts, and rung execution order can matter.

Check how CLICK resolves simultaneous SET and RST instructions

If the same bit is addressed by energized SET and RST instructions during one scan, determine which write controls the result before relying on it for a mode or interlock. The source reports both reset priority and last-executed-instruction priority. Treat that as a decision point, not a rule to guess: inspect the instruction help for the installed CLICK programming software and verify the exact program’s behavior in a safe test.

Observed behavior or symptom	Likely explanation	Next check
The bit is off after both conditions are true	RST priority may apply, or the reset rung may execute last.	Check the rung order and repeat a controlled test with only the relevant writes.
The bit is on after both conditions are true	SET may execute last, or the PLC may apply a different priority rule.	Confirm the actual instruction behavior in the installed software help and test program.
The bit changes unexpectedly scan to scan	Multiple rungs or HMI writes may be competing for ownership.	Find every writer to the bit; assign one owner or make the commands mutually exclusive.

PLC ladder logic evaluates instructions in a scan, and the order and semantics of writes determine the resulting state. A design that depends on simultaneous SET and RST instructions is fragile even if one test appears to produce the expected result. Prefer logic that prevents both commands from being true together or uses a single state assignment path. If this bit controls motion or another hazardous function, stop commissioning until its behavior is deterministic.

Check whether the drum instruction accepts an adjustable time

Do not build cascaded timers first. Inspect the CLICK drum instruction’s configuration and software help for the step-time field: determine whether each step time can reference a variable register or only a configured constant. The HMI can adjust a step duration directly only when the selected instruction and operand support a runtime value. The supplied information does not identify the drum instruction’s time operand, units, or limits, so read those values in the actual project rather than guessing.

1. Open the drum instruction configuration and identify the time field for each step.
2. Check whether the field accepts a variable address that can be written by the HMI.
3. If it does, configure the required variable for steps two and four while leaving steps one and three at their fixed values.
4. If it does not, implement the sequence with separate timers or another supported sequencing method, then verify that each transition advances to the intended step.

When the drum does not expose a runtime-adjustable operand, cascaded timers are a workable fallback, not a requirement to adopt without checking. Keep the timer state and step state aligned: a changed duration must affect the intended step, and the next step must not inherit an old timer completion condition.

Choose one representation for the four-position selector

For off, low, medium, and high, use either a single numeric selection value or a set of PLC-owned target bits. Both approaches represent one selected mode; avoid making four independent toggle states the authoritative mode because they can represent invalid combinations, such as low and high both on.

Representation	How it works	Use it when
Numeric value	The HMI writes a value such as 0 for off, 1 for low, and successive values for the other positions. PLC comparisons select the corresponding logic.	The HMI supports writing a numeric value and the PLC program can validate and decode it.
Target bits	Each momentary HMI command sets its corresponding PLC target bit and resets the other target bits.	The existing program is organized around discrete mode bits.

A numeric value makes exclusivity structurally simple: one register holds one selection. Validate the value before using it; an unsupported or out-of-range value should not silently enable a mode. Target bits can fit an existing ladder design, but every selection path must clear the competing targets. In either design, distinguish the HMI command from the PLC state used to control the machine.

Configure C-More buttons as momentary commands

Use momentary buttons as requests to change the selection, rather than treating each HMI button bit as the lasting machine mode. This avoids depending on a latched HMI toggle to maintain a state that the PLC must arbitrate. The reported C-More Micro behavior also allows the PLC’s RST instruction to return a toggled HMI bit to its off state, but using that feature alone does not solve conflicts among multiple selection buttons.

1. Assign a distinct HMI command bit to each selection, such as the illustrative command bits C0 through C3.
2. Configure each button as momentary, then confirm that a press produces the intended command bit and that releasing it clears the request.
3. Keep the PLC’s final mode state in separate target bits or a separate numeric value; do not use the command bits as the machine’s persistent selection.
4. Check the HMI communication and PLC monitoring screens together so you can see both the command and resulting state.

For a toggle-style HMI button that must return visually to off when another choice is selected, the PLC can reset that HMI bit, as reported for the C-More Micro. Test that reset on the installed panel and project. Prefer momentary command buttons where possible because they make the command’s duration explicit and reduce confusion between a pressed button and an active operating mode.

Map each command to exactly one target state

With target bits, create one selection rung or equivalent logic path per command. The example addresses below are illustrative addresses from the supplied design example, not mandatory addresses: when C0 requests the first choice, set C20 and reset C21 through C23; apply the corresponding set-and-clear pattern for the other commands. Use the target bits—not the transient HMI command bits—for downstream mode logic.

1. On each command, set its matching target bit and reset every other target bit.
2. Check whether two command bits can be active together. If they can, define a deterministic arbitration rule or block simultaneous requests before they reach the selection logic.
3. Find all other instructions that write to the target bits. Remove competing writers or coordinate them through the same selection logic.
4. For a numeric selection instead, decode each allowed value and define the result for the off value and any invalid value.

Setting one target while resetting the others is a common radio-button pattern. It is simpler and safer to reason about than duplicating one-shot toggle logic for every button, provided the command path and all other writes are controlled. Never rely on the HMI display alone to prove that the PLC holds an exclusive selection.

Validate adjustable times before changing a running step

If the drum accepts variable step times, give the operator an HMI numeric entry tied to the supported variable and show the current value. Use the instruction’s configured units and allowable range; read them from the project or CLICK documentation. Add PLC-side range validation so an invalid entry cannot become an unintended duration. Do not enter a guessed maximum, minimum, or unit.

1. Confirm that the HMI write reaches the intended variable by monitoring it in the PLC.
2. Set a known valid test duration and verify that the intended adjustable step uses it.
3. Change the value and confirm the effect occurs at the expected point in the sequence. Determine whether the drum applies a change immediately or at the next step from the instruction behavior; do not assume a running timer reloads automatically.
4. Test the minimum and maximum values permitted by the actual configuration, plus the behavior for an invalid entry.

If the drum only permits fixed times, build and test the fallback timer sequence offline or in a safe commissioning state before connecting it to the machine’s operating outputs. Confirm that fixed steps remain fixed and adjustable steps use the operator-entered values. Keep the production restore separate from the permanent repair: a validated fallback may restore operation, but document and resolve any remaining limitation in the final sequence design.

Verify exclusive selection and step timing at the PLC

Monitor the HMI commands, target bits or selection register, drum step indication, and timer values while testing. Exercise each selection from off and from every other selection; confirm exactly one mode is active after each command and that no command leaves the prior mode energized. If a bit changes unexpectedly, trace every rung and HMI write to it rather than adding another SET or RST instruction.

For timing, run the sequence through all four steps. Check that steps one and three retain their configured durations, that steps two and four use the values entered at the HMI, and that each transition occurs once. Repeat after stopping and restarting the sequence, because stale timer or step state can make a single successful cycle misleading. If any result depends on conflicting writes or undocumented timing behavior, stop the test and resolve it before returning the machine to service.

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