Configuring PCS 7 VlvAnL Setpoint Override Using APL Blocks

1. Problem Overview

In a Siemens PCS 7 V9 system with the Advanced Process Library (APL) V8.0 or later, a control valve driven by the VlvAnL block must accept a manipulated variable (MV) from one of three sources, decided by the state of two binary process signals:

• Binary Signal 1 active → force setpoint A to the valve (highest priority).
• Binary Signal 2 active → force setpoint B to the valve (medium priority, only honored when Signal 1 is absent).
• Neither active → hand the setpoint authority to the operator through the APL faceplate.

This precedence scheme cannot be implemented by wiring a single MV_Ext value directly to the VlvAnL because the operator must retain the ability to type a free setpoint during the no-signal condition. The solution is to combine an APL analog selector block (SelA16In or SelA02In) with the MV_LiOp, MV_ExtLi, and SelExt structure described in the APL Function Manual chapter 6.12 "VlvAnL – control valve".

2. Prerequisites

Before building the CFC, confirm the following engineering workstation and runtime environment:

Import the master data library for your PCS 7 version from the Siemens support portal so the VlvAnL, SelA16In, and SelA02In block icons appear in the CFC catalog under APL → Blocks → Control → Valves and APL → Blocks → Calculation.

3. Block Architecture

The precedence logic is split into two CFCs (or one chart with two pages):

1. Selector CFC — hosts one SelA16In block. Inputs In01 and In02 receive Setpoint A and Setpoint B. The block icon provides an additional manual operator selection through its faceplate.
2. Valve CFC — hosts the VlvAnL block. Its MV_Ext input is wired from the SelA16In output Out. The link enable input MV_ExtLi is driven by an inverted AND of the two binary signals so the operator can freely type a setpoint only when neither signal is active.

For a minimal two-input implementation, the SelA02In block replaces the SelA16In; the Out value equals IN1 when the selection boolean is 1 and IN2 when it is 0. This removes the need for the integer-to-select conversion and is the cleanest design when only two setpoints are required.

4. VlvAnL Block Configuration

The VlvAnL block in APL exposes an interconnected set of mode and manipulated-variable inputs. The four I/Os that matter for external override are:

5. SelA16In Setpoint Routing

Insert a SelA16In block into the Selector CFC. Configure the following I/Os:

• In01 → Setpoint A (REAL, engineering unit)
• In02 → Setpoint B (REAL, engineering unit)
• SelExt → integer from CFC logic:
    – 1 when Sig1 = 1 (Setpoint A wins)
    – 2 when Sig1 = 0 AND Sig2 = 1 (Setpoint B)
    – 0 when Sig1 = 0 AND Sig2 = 0 (operator)
• LiOp → 1 (operator may choose from the faceplate at any time)

If you have the Industry Library installed, the SelI function block selects an integer based on multiple boolean inputs without the need for ladder logic. Without the Industry Library, build the SelExt integer with two AND gates plus an OR:

The output Out is connected to the VlvAnL.MV_Ext input. The SelA16In faceplate exposes In01/In02 values and a manual selection dropdown, which is useful for commissioning but is normally suppressed via operator authorization when Sig1 or Sig2 is active.

6. SelA02In Two-Input Selection (Alternative)

When the design is restricted to exactly two setpoints, the SelA02In block produces a clean analog output from a single boolean:

This avoids the integer conversion in SelA16In and is recommended for greenfield projects where the two-signal structure is fixed by the P&ID.

7. Operator Faceplate and Authorization

The SelA16In block icon and its faceplate remain visible in the OS picture so operators can see which setpoint source is currently routed. Configure the following operator authorizations in WinCC Explorer under User Administrator → Authorization → APL Setpoint Selection:

1. Grant Process controlling only to roles that may override the binary signals (typically only Engineering and Maintenance).
2. Hide the manual dropdown by clearing the OpAut attribute on the faceplate for standard operator roles.
3. Configure an Operator Message on SelA16In.MsgLock so changing the selection during an active override raises an audit-trail entry.

The valve faceplate continues to expose its manual mode entry. Because MV_LiOp is only enabled when both signals are inactive, the operator entry field is automatically de-activated whenever Sig1 or Sig2 goes high — no additional interlock logic is required.

8. Setpoint Limiting

Both Setpoint A and Setpoint B must respect the same high/low engineering limits as the operator entry field, otherwise an external override could drive the valve outside its safe range. Two patterns are commonly used:

1. Source-side limiting: Configure the upstream function block (PID controller or hand-set constant block) with limits Sp_HiLim and Sp_LoLim. The limits are propagated automatically to the SelA16In faceplate read-back.
2. Selector-side limiting: Drop a Limit block (APL: Limit, category Calculation) between the setpoint source and the selector input. Set HiLim and LoLim on the Limit block to the valve-allowed range.

For operator entries, the VlvAnL faceplate already enforces the limits declared on Sp_HiLim and Sp_LoLim. Confirm these limits on the process tag type match the physical actuator stroke (typically 0–100 %). If the engineering unit is volumetric (m³/h), use the same pair of parameters and the same source/selector pattern.

9. Step-by-Step CFC Implementation

1. Create a new CFC chart SETP_SEL_VLV_01 in the plant hierarchy under the unit that owns the valve.
2. Insert the SelA16In block. Name it SEL_SP_VLV_01. Open the block icon properties and confirm Process tag type = SelA16In.
3. Wire In01 to Setpoint A (REAL). Wire In02 to Setpoint B (REAL).
4. Insert two AND blocks and one OR block to compute the integer SelExt. Use the formula in section 5.
5. Insert an AND block with negated inputs (or a NAND + inversion) to compute the inverted AND of Sig1 and Sig2. Wire its output to both VlvAnL.MV_ExtLi and VlvAnL.MV_LiOp.
6. In the valve CFC VLV_01, connect SelA16In.Out to VlvAnL.MV_Ext.
7. Compile the program. In the CFC compiler settings, enable Generate block icons for all blocks so the selector appears on the OS picture.
8. Open WinCC Explorer and run the OS Project Editor to refresh the picture and faceplate references.
9. Download to the AS and OS. Trigger a Compile and Download Objects pass.

10. Commissioning Verification

With the program online, perform the following verification steps in this exact order. Each step assumes the valve is in a safe state and may be blocked by upstream permissives.

Use the CFC online test mode to force individual inputs. Use the OS faceplate Trend view to verify that VlvAnL.MV tracks the selected source with a stable, lag-free response.

11. Troubleshooting Matrix

12. Field-Proven Caveats

• The SelExt integer convention is 1-based (1 selects In01). Off-by-one errors during initial commissioning are the most common cause of inverted routing.
• If the valve is in Tracking mode instead of Auto, the VlvAnL block follows its MV_Track input regardless of the override logic. Confirm the operating mode follower is configured for Auto before testing.
• The APL revision that ships with PCS 7 V9.1 changed the SelA16In default behavior of SelExt when LiOp is low: it now latches the last valid selection. This is normally desirable but can surprise users who expect a fallback to a hardcoded setpoint.
• Watch the alarm External MV invalid raised by VlvAnL. It triggers when MV_ExtLi is high but MV_Ext is out of the configured limits. Suppress this alarm during operator mode if the alarm source is the limit block.
• For redundant AS configurations (AS 410 pair), verify that the SelA16In and VlvAnL blocks are assigned to the same Runtime Group so they switch over consistently during a failover.