Configuring S7-1200 HSC with Omron E6C2-CWZ5B Encoder for Speed

1. Overview

This reference covers configuring a Siemens SIMATIC S7-1200 CPU 1214C high-speed counter (HSC) for an Omron E6C2-CWZ5B incremental encoder (quadrature phases A and B, with index Z) using TIA Portal V11/STEP 7 Basic and the equivalent path in TIA Portal V21. The application produces a direction bit (count up / count down) and a linear speed reading in metres per second from a pulse-train source.

The HSC on the S7-1200 supports four operating modes:

• Single-phase count with internal direction control
• Single-phase count with external direction control
• Two-phase count (quadrature x1, x2, x4)
• Frequency measurement (the mode used for velocity)

For encoder-based speed measurement the HSC is configured for two-phase counting in frequency-measurement mode, where the firmware counts the number of HSC edges detected during a configurable integration window and writes that count to the HSC's process image address (ID1000 for HSC1 on the CPU 1214C).

2. Prerequisites

Before configuring, verify the following:

• CPU: SIMATIC S7-1200 CPU 1214C DC/DC/DC (article number 6ES7214-1AG40-0XB0) or later DC/DC/DC variant. AC/DC/RLY variants have lower HSC limits and are not recommended for encoder inputs above 30 kHz.
• Encoder: Omron E6C2-CWZ5B, NPN open-collector, 12–24 VDC, quadrature A/B + index Z. Confirm the PPR stamp on the encoder body (typical resolutions stocked: 100, 360, 500, 1000, 2000).
• Software: TIA Portal V11 with STEP 7 Basic V11 (for legacy controllers) or TIA Portal V17/V18/V19/V20/V21 for current firmware. The HSC configuration interface is functionally identical across versions.
• Wiring: Shielded twisted-pair cable, encoder case grounded at one end only, 24 VDC supplied to the encoder from the PLC's sensor power terminal.
• Load: Know the linear distance represented by one encoder revolution (wheel circumference, conveyor pitch, lead of a screw, etc.) so the counts-to-engineering-units conversion can be derived.

3. S7-1200 CPU 1214C HSC Hardware Limits

Selecting an HSC channel and an evaluation mode is constrained by the maximum input frequency of the CPU. For the CPU 1214C DC/DC/DC, the limits in the S7-1200 System Manual are:

For an Omron E6C2-CWZ5B with 500 PPR at its rated 6,000 RPM mechanical limit, the maximum pulse frequency is 500 × 6000 / 60 = 50 kHz. With x4 evaluation, the effective count frequency is 200 kHz, which exceeds the 80 kHz HSC limit. Either de-rate the mechanical speed, select x1 evaluation, or move to an encoder with a lower PPR rating.

4. Omron E6C2-CWZ5B Encoder Specifications

The NPN open-collector output sinks current to 0 V when active. To interface with the S7-1200 bi-directional inputs the encoder outputs are pulled up to 24 VDC through 4.7 kΩ resistors on each phase, then wired into the HSC input terminals on the CPU.

5. Wiring Diagram

The NPN open-collector outputs are pulled up to +24 V through 4.7 kΩ resistors at the PLC cabinet terminal block. The PLC inputs are bi-directional (IEC 61131-2 type 3) and register a logic 1 whenever the encoder transistor is OFF (line idles high). When the transistor switches ON, the input is pulled low.

6. TIA Portal HSC Configuration

The configuration procedure differs slightly between TIA Portal V11 (STEP 7 Basic) and TIA Portal V17/V21.

6.1 TIA Portal V11 / STEP 7 Basic

1. Open the project and select the PLC device view.
2. In the device properties, select Digital inputs.
3. Click on the Input filter group and assign the inputs that will be used for HSC1 (default: I0.0 / I0.1).
4. Switch to High-speed counter (HSC) in the same properties panel.
5. Enable HSC1.
6. Set Type of counting to Frequency measurement.
7. Set Operating phase to Two-phase.
8. Set Evaluation to x1, x2, or x4. For maximum resolution at low speed use x4, but check the frequency limit against the encoder's expected maximum pulse rate.
9. Set the Measuring period (integration window). Typical values: 0.1 s for fast response, 1.0 s for smooth output.
10. Assign the input terminals for channels A and B. The Z input can be left disabled if unused.
11. Compile the hardware configuration and download to the CPU.

6.2 TIA Portal V17 / V21

The HSC can still be configured standalone via the CPU properties, but the recommended path for encoder-based motion is to use a positioning axis technology object that consumes the HSC. The relevant option is documented at Encoder on HSC (S7-1200) – TIA Portal V21 documentation:

1. Add a new technology object → TO_PositioningAxis.
2. In Basic parameters → Encoder, select Encoder via High Speed Counter (HSC).
3. Choose the HSC channel (HSC1 – HSC6). The HSC must already be configured for quadrature counting.
4. Set the filter times for both HSC input channels per the encoder signal quality.
5. Define the mechanical configuration: distance per encoder revolution (e.g., π × wheel diameter for a wheel application).

7. CTRL_HSC Instruction

The CTRL_HSC instruction runs the HSC from user logic — typically OB1 (cyclic) or OB35 (cyclic interrupt). It is located in the instructions panel under Technology → Counting.

For a static configuration (period and reference fixed in hardware setup), CV, RV, and PERIOD can be left unwired and only HSC is required.

8. Frequency Measurement Principle

The HSC firmware accumulates HSC edges within a sliding integration window of length T_period. At the end of each window, the count is written to ID1000 (for HSC1) as a DINT, then the accumulator is cleared for the next window.

The instantaneous frequency is therefore:

f (Hz) = ID1000 / T_period (s)

For example: T_period = 1.0 s, ID1000 reads 450 → f = 450 Hz.

9. Converting Counts to Engineering Units (m/s)

The conversion chain from raw count to linear speed follows:

1. Pulse frequency: f = ID1000 / T_period
2. Effective pulses per revolution depends on evaluation:
   • x1: PPR_eff = PPR
   • x2: PPR_eff = 2 × PPR
   • x4: PPR_eff = 4 × PPR
3. Mechanical revolutions per second: n = f / PPR_eff
4. Linear speed: v = n × d_per_rev

Where d_per_rev is the linear distance travelled per encoder revolution. For a wheel of diameter D this equals π × D.

9.1 Worked Example

10. SCL Implementation

The following Structured Text (SCL) snippet reads HSC1 and converts to m/s. Place it in a function block that is called from OB1.

// FB_SpeedFromHSC1
FUNCTION_BLOCK "FB_SpeedFromHSC1"
VAR
    HSC1_Count     : DINT;        // Raw count from ID1000
    PPR            : INT  := 500; // Encoder PPR from nameplate
    EvalFactor     : INT  := 4;   // 1, 2, or 4
    Period_ms      : INT  := 100; // Matches TIA hardware setup
    WheelDiameter_m: REAL := 0.2; // 200 mm wheel
    Frequency_Hz   : REAL;
    Speed_mps      : REAL;
END_VAR

BEGIN
    HSC1_Count   := "ID1000";                       // Read process image
    Frequency_Hz := DINT_TO_REAL(HSC1_Count)
                    / (DINT_TO_REAL(Period_ms) / 1000.0);
    Speed_mps    := Frequency_Hz
                    / (DINT_TO_REAL(PPR) * DINT_TO_REAL(EvalFactor))
                    * (3.14159265 * WheelDiameter_m);
END_FUNCTION_BLOCK

11. Edge Cases and Pitfalls

12. Verification Procedure

1. Watch table test: Add ID1000 and the calculated Speed_mps to a watch table in TIA Portal. Spin the encoder by hand and confirm ID1000 increments with each quadrature edge.
2. Direction test: Reverse rotation. Confirm ID1000 decrements (or speed sign flips).
3. Static reference test: Drive the encoder at a known RPM (use a calibrator or stopwatch). Compute the expected Speed_mps from the formula and compare with the PLC value. Tolerance should be ±2 % at > 10 % of full scale.
4. Frequency limit test: Run the encoder at maximum process RPM. Verify ID1000 increases linearly with speed and does not saturate. If saturation occurs, switch evaluation from x4 to x1 or x2.
5. Edge timing test: Use the HSC's online diagnostic in TIA Portal (Right-click HSC → Online & Diagnostics) to confirm edge counts and capture any reported overflows.

13. Troubleshooting Matrix

14. FAQ