Configuring S7 Clock Memory Pulse-Pause Ratio: A Reference

Overview: What the S7 Clock Memory Byte Is

The Siemens SIMATIC S7 clock memory (German: Taktmerker) is a reserved byte in the CPU's bit-addressable memory area whose eight bits toggle between 0 and 1 at fixed, software-defined frequencies. The ON state and OFF state of every bit are equal in duration, which is the meaning of the documented pulse-pause ratio of 1:1: each bit spends 50% of its period in logic 1 and 50% in logic 0.

The clock memory is generated by the CPU's operating system at the start of every OB1 cycle (priority class 1) and is therefore deterministic with respect to the user program scan. The byte is updated independent of program execution time, so the period you read in the manual is the period you measure at the contact in your ladder logic.

Clock memory is available on every current S7 platform (S7-300/400, S7-1200, S7-1500, and the ET 200S CPU). On the S7-200 the equivalent feature is the Special Memory (SM) bits in the SMB area (e.g., SM0.5 with a 1 s period), and on the LOGO! logic module the function blocks provide equivalent flashing relays.

The 1:1 Pulse-Pause Ratio, Formally Defined

A pulse-pause ratio of 1:1 means that for any given bit n of the clock byte, the time the bit is at logical 1 (pulse) equals the time the bit is at logical 0 (pause). If the period is T seconds, the duty cycle is:

For Bit 7 of the byte, the period is 2.0 s. Therefore the bit is ON for 1.0 s, OFF for 1.0 s, ON for 1.0 s, OFF for 1.0 s, and so on. The same logic applies to every other bit. The ratio is independent of the OB1 cycle time; the operating system toggles the bit when the elapsed time reaches T/2, regardless of whether the user program has just executed or not.

Bit-to-Frequency Assignment Table

The following table is the canonical assignment from the STEP 7 / TIA Portal online help. The byte is treated as a single register; the bits are independent of each other.

All eight frequencies are derived from a single time base by successive division by two (with a single odd divisor for bit 6). The exact internal implementation is firmware-specific, but the documented periods are guaranteed by Siemens for every supported CPU firmware version.

How to Configure the Clock Memory in STEP 7 (Classic)

In STEP 7 V5.x and SIMATIC Manager, the clock memory byte is configured at the CPU properties:

1. Open the S7 Program folder and right-click the CPU (e.g., CPU 315-2 PN/DP).
2. Select Object Properties.
3. Open the Cycle/Clock Memory tab.
4. Tick the Clock memory checkbox.
5. Enter the byte address (commonly MB0, MB10, or MB100; any free M-byte is valid).
6. Click OK and download the hardware configuration to the CPU.

The byte must not overlap with any other used M-byte, with the process-image partition used by the program, or with retentive data that you intend to preserve across a STOP→RUN transition. Clock memory is non-retentive; its state is undefined until the OB1 cycle resumes.

How to Configure the Clock Memory in TIA Portal (S7-1200 and S7-1500)

1. In the project tree, expand the S7 device and double-click Device configuration.
2. Select the CPU in the device view.
3. In the inspector window, open Properties > System and clock memory (S7-1500) or Properties > Cycle (S7-1200).
4. Tick Enable clock memory byte.
5. Enter the Clock memory byte address (default often MB0; Siemens recommends an address in the range MB10–MB199 for S7-1500 to avoid overlap with optimized data and system bytes).
6. Compile and download the hardware configuration.

Cross-Reference: Same Feature, Different Platforms

Typical Use Cases

The clock memory byte is intended for low-bandwidth periodic events where the exact phase relationship to OB1 is unimportant. Common applications include:

• Flashing beacons and indicator lamps (Bit 5 at 1.0 s is the canonical 1-second flasher).
• Heartbeat / life-bit monitoring: ladder code monitors one bit and raises an HMI alarm if it stops toggling for more than twice the period.
• Stochastic sampling: sample an analog value every 0.1 s (Bit 0) to capture fast temperature or pressure transients without engaging the full PID controller.
• Long-period clocks for operators (Bit 7 at 2.0 s) used as a cadence for machine status display.
• Watchdog reset for sub-systems that require a periodic handshake.
• Triggering periodic jobs in OB35 / cyclic interrupts when you do not want to configure a dedicated OB35 interval.

Example: LAD snippet that flashes Q0.0 at 1 Hz

Network 1:
      M 5.0         Q 0.0
   |--|/|----------( )--|
      (clock bit 5 = 1.0 s period)

Because the duty cycle is exactly 50%, the contact M5.0 closes for 1 s and opens for 1 s, producing a 1 Hz square wave on the output.

Example: SCL block that toggles a 2 Hz heartbeat for an HMI tag

IF "Clock_Memory_Byte".%X3 THEN      // Bit 3 = 2 Hz
    "HMI_Heartbeat_OK" := TRUE;
ELSE
    "HMI_Heartbeat_OK" := FALSE;
END_IF;

The Restart Phase-Offset Problem (Critical Edge Case)

Engineers frequently try to use clock memory as a free timer replacement by counting edges. The field report surfaces an important limitation: the phase of every clock bit is undefined at STOP→RUN.

Concretely, if you wire Bit 5 (1.0 s period) to a counter, the first edge after restart can arrive anywhere from 0 ms to 1000 ms after the CPU enters RUN, depending on what phase the OS scheduler was in at the moment of the transition. Over many restarts the average error is half the period (0.5 s for Bit 5), and the worst case is a full period (1.0 s).

This is acceptable for indicator lamps and watchdog handshakes but is not acceptable for any measurement where you need an absolute time reference (e.g., "measure temperature every 60 seconds exactly"). Use a true cyclic interrupt OB instead:

Sample-ST Code: Edge-Counting with Restart Correction

If you must use clock memory for an edge counter, correct for the phase offset on startup. The following SCL block in an S7-1500 waits for the first 0→1 transition of Bit 5 and then re-syncs a 1-second IEC timer.

REGION EdgeCounter
    // Detect rising edge of clock bit 5 (1 Hz)
    IF "Clock_Byte".%X5 AND NOT "Edge_Memory" THEN
        "Edge_Count" := "Edge_Count" + 1;
        // First rising edge after RUN: start a 1 s IEC timer to lock phase
        IF NOT "Phase_Locked" THEN
            "Phase_Locked" := TRUE;
            "Phase_Timer" (IN := TRUE, PT := T#1S);
        END_IF;
    END_IF;
    "Edge_Memory" := "Clock_Byte".%X5;

    // Phase-locked IEC timer replaces free-running counter
    IF "Phase_Timer".Q THEN
        "Phase_Timer" (IN := FALSE);
        "Locked_Pulse" := NOT "Locked_Pulse";
    END_IF;
END_REGION

This pattern eliminates the 0–1 s startup error because the IEC timer is started from the first observed clock edge; all subsequent pulses are aligned to that phase.

Interactions with Process Image, Retain, and Optimized Access

• Process image (PII / PIQ): Clock memory is updated by the OS at the start of OB1. Bits reside in the bit memory (M) area and are visible to all program blocks without explicit PI loading.
• Retain attribute: Clock memory is implicitly non-retentive. The retain setting on the M-byte is ignored for the clock byte. Do not mark the clock byte as retentive.
• Optimized block access (S7-1500): You cannot declare M as a fully optimized area. Access the clock byte through a global DB with standard (non-optimized) access, or address MB<n> directly via the absolute name.
• HMI polling: HMI tags pointed at the clock byte generate high HMI traffic because every poll sees the bit toggling. Limit the polled area to non-toggling bits, or use a heartbeat tag derived in the PLC code (e.g., an M-bit that mirrors clock bit 5).

Verification Procedure

1. Download the hardware configuration with the clock byte enabled.
2. Open an online watch table in STEP 7 / TIA Portal and add the clock byte as a binary display.
3. Force the CPU to RUN if not already running.
4. Confirm Bit 5 toggles every 1.0 s ±10 ms (the tolerance is bounded by the OB1 cycle).
5. Measure Bits 0 (0.1 s) and Bit 7 (2.0 s) for the bookends.
6. Trigger a STOP→RUN transition and observe Bit 5: it must resume toggling, but the next edge may arrive up to 1.0 s after RUN.
7. Verify that no other code is writing to MB<n> — a stray MOVE or SET coil anywhere will break the toggling.

Troubleshooting Matrix

Field-Commissioning Checklist

• Clock memory enabled in CPU properties and downloaded.
• Clock byte address documented and unique to clock function (no overlap).
• Watch table confirms Bit 5 toggles at 1 Hz, Bit 0 at 10 Hz, Bit 7 at 0.5 Hz.
• Program code does not write to the byte.
• No optimized-block conflicts on S7-1500.
• HMI tags are limited to relevant bits to avoid wasted bandwidth.
• Counter-based applications either accept the ±0.5 T phase error or use a phase-locked IEC timer.
• Restart behavior observed and documented in the project functional specification.

Related Functions Worth Knowing

• Time-of-day interrupts (OB10): for absolute scheduling, e.g., "run report at 23:59 every Sunday".
• Cyclic interrupts (OB30–OB38): for high-priority periodic tasks; selectable phase and period from 1 ms to 60 s depending on CPU.
• Hardware timer DI / DO modules: for high-frequency counters independent of the OB1 scan.
• PWM / PTO outputs: for variable duty cycle and pulse-train applications (NOT 1:1 ratio).
• IEC timers (TP, TON, TOF, TONR): for general timing inside user program blocks.