Configuring Siemens PCS 7 APL Library Blocks: Reference Guide

The SIMATIC PCS 7 Advanced Process Library (APL) is the canonical block set for continuous and batch process automation on AS 410 / AS 410E / AS 410 SMART stations. Every motor, valve, PID controller, analog input, and digital output in a PCS 7 project is built from APL block types, and the field behavior of those blocks is driven by the I/O signals you wire in CFC (Continuous Function Chart) and SFC (Sequential Function Chart). This reference collects the block catalog, the input/output conventions, the documentation set, and the commissioning checks you need to configure APL blocks correctly on PCS 7 V7.1 SP2 and later, including the V9.1 release line.

1. PCS 7 Library Architecture Overview

PCS 7 ships three logically separated block libraries that the Engineering System (ES) loads into the master data library:

The APL block types are faceplates and alarm-ready by design. Each block instantiates an @APL_S_xxx symbol in the S7 program and exposes a faceplate to WinCC Runtime through the same block instance. When you drop FB1869 "CTRL_PID" into a CFC chart, the runtime automatically generates the trend view, message view, and standard view faceplate elements.

2. APL Block Catalog by Function Class

The APL is organized into 16 function classes that mirror the engineering phases of a process plant. The table below lists the block types that appear in the V9.1 Industry Library manual and the corresponding PCS 7 APL master data library. Each block is a Function Block (FB) with a fixed Instance DB and a generated SFC source.

The Industry Library V9.1 manual is published as PCS 7 Industry Library for PCS 7 (V9.1) and contains the same 16 function classes with added domain-specific block types (e.g., PUMP_C, TANK_L, BELT_W, REACTOR_TEMP).

3. Documentation Set for PCS 7 Block Library Use

Siemens publishes the documentation as a layered manual set. Use the references below in the order listed when you are new to PCS 7 block wiring.

1. Getting Started Part 1 (as of V8.0 with APL) - SIMATIC PCS 7 Getting Started Part 1 - step-by-step engineering of a sample project from hardware configuration through WinCC commissioning.
2. Getting Started Part 2 (as of V8.0 with APL) - SIMATIC PCS 7 Getting Started Part 2 - extends the sample project with SFC sequencing, batch, and operator screens.
3. PCS 7 Compendium Part A - PCS 7 Compendium A - full project setup A to Z, including plant hierarchy design, master data library use, and signal-flow patterns.
4. Standard Blocks Manual (legacy) - PCS 7 Standard Library Blocks Manual - block-by-block I/O description for the IFL/Standard Library. Still required when you must maintain a V7.1 SP2 project.
5. PCS 7 CFC for SIMATIC S7 - working with CFC charts, inter-chart connections, run-time groups, and chart partitioning.
6. PCS 7 Programming Instructions for Blocks V7.0 and higher - rules for naming conventions, instance DB layout, and block icon generation.
7. PCS 7 Industry Library V9.1 PDF - PCS 7 Industry Library for PCS 7 (V9.1) - block catalog for IL with V9.1-specific function classes.

4. How APL Block Connections Are Structured

Every APL block has the same input/output anatomy. The figure below describes the standard layout of an APL I/O block (the structure is identical for motor, valve, and controller blocks with small additions).

4.1 Universal I/O Structure

4.2 Block Connection Flow

Wiring an APL block is performed in three steps inside the CFC editor. The same flow applies whether the block is in the unit-level UNIT chart or a process tag chart under PLANT_HIERARCHY\Area\Unit\Chart.

1. Drag the block type from the APL master data library into the CFC sheet. The block is instantiated with a default name such as MOT_001.
2. Right-click the block and assign an S7 tag name. The naming convention is the chart path plus instance: AREA1\UNIT_A\MTR_PUMP1.MOT_001.
3. Wire the I/O pins to either chart-level shared addresses (inter-chart connection through Chart I/O view) or directly to the field via a CH_AI / CH_AO / CH_DI / CH_DO channel driver block.

5. Standard Block Wiring Patterns (Templates)

PCS 7 ships a Templates folder inside every APL master data library. The templates are pre-wired CFC sheets that you copy into your project. The list below covers the templates present in the V9.1 Industry Library set and the standard APL set.

6. Step-by-Step Configuration Procedure

6.1 Prerequisites

• PCS 7 Engineering System installed (V7.1 SP2 / V8.x / V9.x) on Windows 10 / Server 2016 or later.
• STEP 7 V5.5 SP4 (for V7.1 SP2 projects) or STEP 7 V5.6 SP2 (for V8.x) installed on the ES.
• Master data library with the correct APL version (e.g., PCS7_APL_V91) loaded in SIMATIC Manager under Options > Master Data Library > Open.
• Plant hierarchy created with at least one AREA, one UNIT, and a process tag Chart container.
• Hardware configuration for the AS 410 family (or AS 410E / AS 410 SMART) compiled successfully.

6.2 Insert a Motor Block from the APL Library

1. Open the target CFC chart in PLANT_HIERARCHY\AREA1\UNIT_A\MTR.
2. From the Library task card, navigate to PCS7_APL_V91\Blocks+Templates\Blocks\Motors.
3. Drag MOT (FB1650) into the CFC sheet. The block lands at the next free grid position.
4. Right-click the block icon, choose Object Properties > Block, and set:
   • Name = MOT_PUMP1 (8-character S7 limit)
   • Instance DB = DB1201
   • Comment = Boiler feed pump 1 - forward running
5. Open the Chart I/O view and expose the following pins as chart inputs/outputs:
   • Input: SP_AUT (start command, BOOL)
   • Input: SP_REM (remote start, BOOL)
   • Input: INT_LOC (interlock, BOOL)
   • Output: Q_RUN (running status, BOOL)
   • Output: Q_FAULT (motor fault, BOOL)
6. Compile the chart with Chart > Compile > S7 and check the diagnostic buffer for FB/DB signature mismatches.

6.3 Wire the Channel Driver

1. Insert CH_DO (FB240) for the start command. Connect its OUT to the digital output module address (e.g., QW0 bit 0 of slot 4).
2. Insert CH_DI (FB241) for the running feedback. Connect its IN to the digital input module address (e.g., IW0 bit 0 of slot 4).
3. Insert a second CH_DI for the thermal overload / fault contact.
4. In the CFC sheet, draw the connections:
   • CH_DO.OUT → MOT_PUMP1.SP_AUT
   • CH_DI_RUN.IN → MOT_PUMP1.FB_RUN
   • CH_DI_FLT.IN → MOT_PUMP1.FB_FAULT
5. Right-click the connection lines, choose Connection > Properties, and set the Signal Flow direction (the APL blocks require the flow to point from the field driver to the block input).

6.4 Configure the Faceplate in WinCC

1. Open the WinCC Explorer of the OS project.
2. Run OS Project Editor > Faceplate Assignment. The OS Project Editor reads the SFC and CFC instance data and assigns the APL faceplates automatically.
3. Verify the faceplate appears in the unit's process image. Right-click the block instance, choose Picture > Open Faceplate. The MOT faceplate must show the standard view with Start, Stop, Local/Remote, Auto/Manual, Acknowledge, and the limit value strip.

7. Block-Specific Configuration Notes

7.1 CTRL_PID (FB1869) - Continuous Controller

7.2 MOT_SPD (FB1661) - Variable-Speed Motor

Use MOT_SPD for drives controlled via PROFIdrive (SINAMICS G120, G150, S120) over PROFIBUS DP or PROFINET. The block expects three PROFINET/PROFIBUS data words (control word 1, control word 2, speed setpoint) and produces three data words back (status word 1, status word 2, speed actual). The block's SPD_AUT and SPD_REM inputs accept the setpoint source, and SPD_FBK returns the measured speed.

7.3 VALVE_ANA (FB1665) - Modulating Valve

The modulating valve block has two important interlocks built in:

• INT_LOC blocks the valve from moving in any mode.
• PERM_ON must be TRUE for OPEN movement; PERM_OFF must be TRUE for CLOSE movement. Leave both FALSE to disable the valve without triggering an interlock message.

Positioner fault detection: if the difference between MV and PV exceeds POS_DIFF for longer than POS_T, the block raises a positioner fault alarm. Default values: POS_DIFF = 5%, POS_T = 30 s.

7.4 AIN (FB7) / AOUT (FB9) - Channel Blocks

Configure the channel blocks through their CH_CFG input. For 4-20 mA signals:

• CH_CFG.VAL_TYPE = 1 (4-20 mA linear)
• CH_CFG.HIGH_SCALE = 100.0
• CH_CFG.LOW_SCALE = 0.0
• CH_CFG.SIM_ON = FALSE (simulated value for commissioning)

8. Verification and Commissioning Checks

1. Compile CFC: Chart > Compile > S7. The "Compile" tab must show zero errors and zero warnings. Open the Compile Log and confirm the FB/DB block list matches the project master data library version.
2. Download to AS: Use PLC > Download > Entire Program. The AS must be in STOP. Verify the online view shows the block instances with the correct runtime version (e.g., FB1869 v2.0 for CTRL_PID V9.1).
3. OS Project Editor: Run the OS Project Editor with Re-Generate All Pictures enabled. Open the runtime image and confirm every APL block icon has an active faceplate link.
4. Watch Table Test: Open a watch table on the AS online view, force the digital outputs to TRUE one at a time, and confirm the faceplate in WinCC switches from AUT to MAN and the runtime trend updates within the configured refresh time (default 1 s).
5. Alarm Test: Trigger an interlock violation (e.g., force INT_LOC = FALSE while the motor is running). The OS message line must display a Class "Interlock" alarm with the configured acknowledgment model.
6. PID Tuning: Put CTRL_PID in manual, step the MV by 10%, observe the PV response, then switch to auto and tune Kp, Ti, Td. Tune using the standard Ziegler-Nichols step or Lambda tuning. Keep Ti ≥ 5 * sample time to prevent integral windup.

9. Troubleshooting Matrix

10. Library Version Migration Path (V7.1 SP2 → V9.1)

Projects that originate on V7.1 SP2 with the IFL/Standard Library require a structured migration. Siemens supports two approaches:

1. Drag-and-drop replacement (small projects): In the CFC, delete the IFL motor block, drag in the APL MOT block, manually rewire the 6-8 standard I/O pins, and recompile. This is acceptable for fewer than 50 blocks per AS.
2. Migration tool (large projects): Use Options > PCS 7 > Library Migration. The tool reads the IFL block signatures and substitutes the matching APL V9.1 block type, preserving the instance DB names, the CFC connection list, and the OS faceplate assignment.

After migration, recompile both the AS and OS, perform a full S7 download, regenerate the OS pictures, and run a controlled alarm test on every migrated block before taking the affected unit back into production.

11. Performance and Cycle-Time Considerations

Every APL block consumes runtime on the AS cycle. A typical AS 410 station (CPU 410-5H, firmware V8.2 or later) supports roughly 300 blocks per OB1 cycle at a 100 ms cycle time. Heavy use of CTRL_PID, MOT_SPD, and VALVE_ANA blocks with long list of alarms increases OB1 load significantly. Apply these rules:

• Group fast interlocks (less than 50 ms response) in the OB1 run sequence.
• Place slow controller loops (1-2 s) in OB35 or OB36 with their own run-time group.
• Use PHASE in the CFC run-time group to offset the start of each block family and avoid spike loads.

12. Frequently Asked Questions