Converting S7-200 SM0.3 to S7-1200 First Scan and Clock Memory Bits

When migrating STEP 7 Micro/WIN projects to TIA Portal on the SIMATIC S7-1200, two of the most commonly missed signals are the power-up first-scan bit (SM0.3) and the runtime clock bits (SM0.4 / SM0.5). Engineers routinely wire these into coil logic expecting a pulse, then watch the Q output either stay high continuously or stay dark entirely. This reference explains the exact mapping, the configuration that enables the S7-1200 equivalents, and the edge-detection pattern required to convert the cycling clock waveform into a clean one-shot pulse.

Overview: Why the S7-200 Conventions Don't Carry Over

The S7-200 (CPU 21x and 22x families) reserves fixed special memory (SM) bytes for system status. SM0.0 is "Always_On," SM0.1 is "First_Scan_On," SM0.3 is "Power_Up" (a single positive pulse on the first scan after entering RUN), and SM0.4 / SM0.5 are the 1-minute and 1-second clock bits with 50 % duty cycle. These addresses are wired into the S7-200 firmware and are always active.

The S7-1200 (CPU 12xx and 15xx families) does not expose fixed SM addresses in the same way. Instead, TIA Portal exposes equivalent functions through the standard marker (M) area, and you must explicitly enable the clock memory inside the device configuration. Forgetting to enable it is the single most common reason a lamp wired to %M0.5 never flashes. The first-scan bit, by contrast, is enabled automatically as long as the default startup OB is present in the project.

Special Memory Bit Mapping Table

Configuring the First Scan Bit (%M1.0) on S7-1200

%M1.0 is automatically driven by the S7-1200 startup routine. Unlike most other system bits on the platform, no project setting is required to enable it. The bit is set TRUE for exactly one OB1 pass after every STOP → RUN transition, then remains FALSE until the next power-up or restart. To use it, simply reference it in your logic.

1. Open your TIA Portal project and expand the Program blocks tree.
2. Open OB1 (Main) or insert a new FC / FB if you prefer structured code.
3. Insert a normally-open contact and address it to %M1.0.
4. Wire the contact to a coil, an FB call, or a SET / RS instruction.
5. Download the project to the CPU and switch the CPU from STOP to RUN.
6. In online view, verify that %M1.0 shows TRUE for exactly one OB1 pass after startup, then FALSE for the remainder of the cycle.

LAD Example — First Scan Latch

Network 1: One-shot on first scan (set latched bit)
|--[ %M1.0 ]--( S %DB1.DBX0.0 )--|

Network 2: Manual reset
|--[ %I0.0 ]--( R %DB1.DBX0.0 )--|

Network 3: Drive lamp from latched bit
|--[ %DB1.DBX0.0 ]--( %Q0.0 )--|

SCL Equivalent

IF "M1_0_FirstScan" THEN
   "FirstRunDone" := TRUE;
END_IF;

IF "I0_0_Reset" THEN
   "FirstRunDone" := FALSE;
END_IF;

"Q0_0_Lamp" := "FirstRunDone";

Configuring Clock Memory Bits in TIA Portal

The clock memory block is disabled by default. Until you enable it, the marker bytes you try to read are static zeros — which explains the classic symptom of "lamp never pulses."

1. In the project tree, select the CPU (e.g., CPU 1214C DC/DC/DC, order number 6ES7 214-1AG40-0XB0).
2. Open Properties → System and clock memory (German: System- und Taktmerker).
3. Tick Enable the use of clock memory byte.
4. Enter the byte address; the default is %MB0. The eight bits are then mapped as follows:

For S7-1200 firmware V4.x and later, the clock memory is generated from the system tick and is not affected by the user program cycle time. On firmware V3.0 and earlier the frequencies were tied to OB1 cycle time and could drift.

The Clock Memory "Pulse" Problem

Directly wiring %M0.5 to a Q output produces a 1 Hz square wave, not a one-shot pulse. The coil energises for 500 ms and de-energises for 500 ms. If your intent is "toggle the lamp once every second" that may be acceptable; if your intent is "fire the lamp once when the clock goes high," you need a positive-edge (P) trigger or a TP timer.

The S7-200 generated SM0.5 as a 50 % duty-cycle signal; SM0.3 was the only one-shot edge. Engineers migrating code often mistakenly wire SM0.5 into logic that previously used SM0.3 and assume the result will be a pulse. It will not. The lamp will simply blink at the clock frequency.

Solution 1: P (Positive Edge) Contact in LAD / FBD

The simplest fix is to place a positive-edge-detecting contact in series with the clock bit. The contact conducts exactly once per low-to-high transition of the clock, regardless of how long the input remains high. The internal edge memory is hidden inside the contact — no extra variable is needed.

Network 1: One-shot pulse from 1 Hz clock
|--|P|--( %M10.0 )--       ; P contact addressed to %M0.5
       (Operand: %M0.5)

In TIA Portal, insert the contact from the bit-logic palette under Edge detection. Address the operand to %M0.5. Each rising edge of %M0.5 sets the coil TRUE for exactly one OB1 scan.

FBD Equivalent

[%M0.5] >|P|> [%M10.0]

SCL Equivalent (manual edge)

IF "Clock_1Hz" AND NOT "Edge_Memory" THEN
   "Pulse_Output" := TRUE;
ELSE
   "Pulse_Output" := FALSE;
END_IF;
"Edge_Memory" := "Clock_1Hz";

Solution 2: TP (Pulse Timer) Instruction

The TP instruction from the Timers palette generates a fixed-width pulse on every rising edge of its input. This gives you deterministic pulse width regardless of clock frequency — useful when you want a 200 ms pulse from a 1 Hz clock or a 50 ms pulse from a 10 Hz clock.

LAD Network with TP

Network 1: 500 ms pulse on every rising edge of 1 Hz clock
|--[ %M0.5 ]--[ TP %DB_TP ]--[ %M10.0 ]--|
|              PT: T#500ms                 |

Network 2: Drive the lamp
|--[ %M10.0 ]--( %Q0.0 )--|

The TP block must be instantiated in a data block (either an instance DB or a global DB). Place a single instance DB "TP_DB" under Program blocks → Add new block → DB and reference it in the call.

Solution 3: Dedicated Pulse Generator from OB1 Cycle

If you want a free-running one-second pulse without using the clock memory, derive it from a cycle counter:

// SCL — 1-second pulse from 10 ms OB1
IF "CycleCounter" >= 100 THEN
   "Pulse_1s" := TRUE;
   "CycleCounter" := 0;
ELSE
   "Pulse_1s" := FALSE;
   "CycleCounter" := "CycleCounter" + 1;
END_IF;

This pattern is cycle-time dependent. If you change the OB1 watchdog or the program grows heavy, the pulse width drifts. For timing-critical applications, always prefer the hardware-derived clock memory plus a TP timer.

Hardware Considerations: Signal Module Installation

If your migration also involves expanding the I/O with signal modules (SM 1221, SM 1222, SM 1223, SM 1231, SM 1232), follow the manufacturer installation procedure. Power must be removed from the CPU and all SMs before any module is connected or removed. Retract the bus connector on the right side of the CPU, align the SM on the DIN rail, and lock the bus connector so the module seats against the CPU's contacts. Reapply power only after all modules are mechanically secured.

Reference: SIMATIC S7-1200 Manual Collection — Installing and Removing an SM.

Bit-Logic Edge Reference for S7-1200

Retentive vs Non-Retentive Marker Considerations

The S7-1200 marker area is split into retentive and non-retentive ranges. By default, %MB0 through %MB15 are retentive on most CPU 12xx models, although the exact split can be changed under Properties → Retentive memory. The clock memory byte should remain in the non-retentive portion so its pattern restarts cleanly after a power cycle. Avoid placing process-critical latches inside %MB0 — they will be overwritten by the clock bits at runtime.

If your migrated S7-200 code used SM0.3 to clear initialisation flags, replicate the pattern with a SET / RS block driven by %M1.0, not by the clock memory. The clock memory is continuously running and will re-fire your init routine every 0.5 s if you wire it incorrectly.

Verification and Commissioning Checklist

1. Open the project online with TIA Portal connected to the CPU.
2. In a watch table, monitor %M1.0. Trigger a STOP → RUN transition and confirm %M1.0 is TRUE for exactly one OB1 cycle, then FALSE.
3. Confirm %MB0 is enabled in the device configuration; observe %M0.5 toggling at 1 Hz in the watch table.
4. Insert a |P| (positive-edge) contact in front of the lamp coil and verify the lamp now pulses once per second instead of blinking continuously.
5. Cross-reference the diagnostic buffer for OB-startup errors; an empty or deleted startup OB will silence %M1.0.
6. Verify the pulse width with a TP instruction by reading the ET (elapsed time) tag against expected PT (preset time).
7. Power-cycle the CPU and confirm the first-scan bit re-fires on the next RUN transition.
8. Force %M0.5 = 0 and verify the |P| contact does not re-trigger — confirms edge memory is functioning.

Troubleshooting Matrix

Migration Pattern Summary

Three rules cover 90 % of S7-200 → S7-1200 special-memory migrations:

1. SM0.3 → %M1.0 — first scan, automatic, requires startup OB.
2. SM0.5 → %M0.5 — clock memory, requires explicit enable in device configuration.
3. Any direct coil drive from a clock bit needs a P-contact or TP timer to behave as a one-shot.

Apply these three rules and the classic "SM0.3 doesn't work on S7-1200" migration question disappears.

Frequently Asked Questions