CPU 1512SP vs S7-1200 1214C: Sizing 25 PID Temperature Loops

Selecting a SIMATIC controller for a multi-zone thermal process (heat-treat furnace, plastic-extrusion die, hot-plate battery, environmental chamber) usually starts with one question: can the CPU sustain 25 PID loops at the scan time the process demands? This reference sizes the two controllers most often proposed for this workload - the S7-1200 CPU 1214C DC/DC/DC (6ES7214-1AG40-0XB0) and the ET 200SP CPU 1512SP-1 PN (6ES7512-1DK02-0AB0, 200 KB program / 1 MB data) - and walks through the cyclic-interrupt, phase-shift, and memory-budget decisions needed to land on a defensible choice.

1. Problem Statement & Control Architecture

The target application is 25 independent heat-only temperature zones. Each zone contains:

• One PT100 (RTD, 2- or 4-wire) measuring the workpiece or platen temperature.
• One control element (analog 0-10 V or 4-20 mA to a thyristor power controller driving a resistive heater).
• One PID loop with a target scan time of 300 ms (matches the dominant time constant of typical heated masses: thermal τ in tens of seconds, disturbance spectrum well below 1 Hz).

There is no cascade and no master/slave relationship. The user program is supervisory only: it writes setpoints, monitors alarms, and handles mode changes. The 25 PIDs are the dominant CPU load.

The two candidate controllers differ significantly in:

• Work memory for code and instance data.
• Bit-instruction throughput - relevant because each PID block runs sequentially inside its cyclic-interrupt OB.
• Number of cyclic-interrupt OBs available for distributing PID execution.

Each candidate is evaluated against (a) fitting 25 PID instances into work memory, (b) sustaining a 300 ms effective PID sample time under all 25 loops, and (c) leaving CPU headroom for the supervisory program and PROFINET diagnostics.

2. CPU Candidates: Specifications & Catalog Numbers

Specifications are taken from the S7-1200 System Manual (109754400) and the ET 200SP System Manual (58649293). Confirm the firmware release against the Siemens Industry Online Support entry for your specific MLFB before ordering.

3. PID Block Selection: PID_Compact vs PID_Temp

TIA Portal ships three PID libraries; the right one for 25 heat-only zones is the trade-off between footprint, autotune capability, and pre-conditioning for thermal processes.

PID_Temp is the technical first choice for heat-only processes because it includes:

• Anti-windup, derivative filter, and setpoint ramp shaping sized for thermal time constants.
• Pretuning and tune in running wizards that converge from a cold-start in a few cycles.
• Two auxiliary outputs (OutputHeat, OutputCool) that can be wired to the same analog output if cooling is not used.

See the PID_Temp block description (108591596) for parameter details. If footprint is the binding constraint, fall back to PID_Compact; the user is giving up the temperature-specific tuning heuristics, not basic loop closure.

4. Memory Budget for 25 PID Instances

A back-of-envelope memory budget decides the choice before cycle-time is even considered.

Memory budget (PID_Temp):
  25 instances x 2.5 KB (avg instance DB) = 62.5 KB
  + 1x PID_Temp FB code (shared)         approx. 50 KB
  + 1x PID_Compact FB (auxiliary)        approx.  8 KB
  + supervisory logic, alarms, I/Os      approx. 25 KB
  --------------------------------------------
  Total program memory                   approx. 145 KB

The 1214C's 100 KB work memory cannot host 25 PID_Temp instances plus a normal supervisory program. Even compressing to PID_Compact:

Memory budget (PID_Compact):
  25 instances x 1.0 KB                = 25 KB
  + 1x PID_Compact FB code (shared)    approx.  8 KB
  + I/O mapping, alarms, OB1 logic     approx. 15 KB
  --------------------------------------------
  Total                                approx.  48 KB

Compiles into the 1214C, but only if the user is disciplined about no extra blocks. The 1512SP's 200 KB program memory accepts PID_Temp with comfortable headroom for future expansion. If the work envelope is fixed at 100 KB, you must use PID_Compact - and accept that autotune will be the generic PID_Compact variant rather than the temperature-tuned PID_Temp.

5. Cyclic-Interrupt Architecture (OB30–OB38)

Cyclic-interrupt OBs are the right execution container for PID blocks. They run at a fixed, hardware-time-stamped interval independent of OB1's scan - critical when the PID sample time must remain constant regardless of how busy the main scan is.

Both CPUs support nine cyclic-interrupt OBs: OB30 through OB38. Each OB has a configurable cycle time (1 ms to 60 000 ms) and a phase offset (0 to 30 000 ms). The phase offset staggers multiple cyclic OBs so that they do not all fire at the same instant.

Each cyclic OB runs five PID instances. With five OBs staggered at 20 ms intervals, the CPU sees one OB every 20 ms - never a spike of 25 PIDs at once. Each individual PID block is called every 100 ms; the PID block's internal CycleTime parameter is then set to 0.3 s (3 × OB cycle) so the output updates only every third call, which is the desired 300 ms effective sample time.

6. Phase-Shift Load Distribution

Phase shifting is the single biggest performance lever for multi-PID CPUs. Without it, OB30 fires every 100 ms and processes 5 PIDs in a 5–10 ms burst; OB31 fires immediately after, creating a CPU-load envelope of 5 PIDs every 100 ms, no smoothing. With 20 ms phase offsets, the load envelope becomes 1 OB every 20 ms, with each OB doing 1/5 of the total work. Worst-case cycle-time jitter is reduced by 5× and the OB1 main program is never starved.

Fig. 1 - Five cyclic-interrupt OBs staggered at 20 ms intervals, distributing 25 PID evaluations evenly across the 100 ms fundamental period.

Implementation: in TIA Portal, create five cyclic OBs (Add new block > Organizational block > Cyclic interrupt). Open the OB's properties and set:

OB30: Cycle time = 100 ms, Phase offset = 0  ms
OB31: Cycle time = 100 ms, Phase offset = 20 ms
OB32: Cycle time = 100 ms, Phase offset = 40 ms
OB33: Cycle time = 100 ms, Phase offset = 60 ms
OB34: Cycle time = 100 ms, Phase offset = 80 ms

7. PT100 Signal Conditioning & RTD Module Selection

PT100 inputs in TIA Portal are wired through dedicated RTD modules - never through standard analog inputs. Use the SIMATIC module selection that matches the line length and the required accuracy.

Twenty-five PT100 channels need 7 modules in either series (4 ch × 7 = 28 channels, 3 spare for redundancy). Wire the RTD in 4-wire configuration to eliminate lead-resistance error:

Fig. 2 - 4-wire RTD wiring eliminates lead-resistance error; I+/I- carry the excitation, I0a+/I0a- sense the voltage drop directly at the PT100 element.

In TIA Portal, configure the RTD module's channel with the following parameters to match the application:

Measurement type    : RTD thermal resistance
RTD type            : Pt 100 (standard climatic range)
Temperature unit    : °C
Temperature range   : -200 ... +850 °C
Smoothing           : 4 (or higher if the PT100 lead is electrically noisy)
Noise rejection     : 50 Hz (mains frequency match)
Wire break detection: enabled

8. Analog Output & Heater Actuator Wiring

The user specified analog output to the heater driver, which is the most flexible approach (continuous phase-angle or burst-firing SCR power controllers). Output range is 0–10 V or 4–20 mA; the SCR unit determines which one.

For 25 zones, use seven 4-channel AQ modules. Configure each channel for 0–10 V (unipolar) unless the SCR unit requires 4–20 mA for long cable runs. Map the PID's OutputHeat to the raw analog word and set the output scaling in the channel configuration (default 0–27648 corresponds to 0–10 V).

Fig. 3 - Heat-zone signal flow: CPU PID_Compact → analog output → SCR power controller → resistive heater. PT100 closes the loop on the temperature feedback path.

9. TIA Portal Configuration Procedure

1. Hardware configuration. Add the CPU and the I/O modules to the device view. For ET 200SP: slot the CPU 1512SP first, then add BaseUnits (BU15-P16+A0+2D, 6ES7193-6BP00-0DA0) for each I/O module. Configure PROFINET network parameters (IP, subnet mask, gateway, device name).
2. Insert cyclic OBs. Project tree → PLC → Program blocks → Add new block → Organizational block → Cyclic interrupt. Repeat five times for OB30 through OB34.
3. Configure cyclic OB properties. For each OB, open Properties → Cycle / Phase offset. Set Cycle time = 100 ms, Phase offset = 0, 20, 40, 60, 80 ms respectively. Keep priority at the default 16.
4. Add PID blocks. Project tree → Technology → PID Control → PID_Compact (or PID_Temp) → Add new instance. Repeat 25 times, one per zone. In the configuration dialog, assign each PID to one of the five OBs (five PIDs per OB).
5. Set PID sample time. For each instance, open Configuration → Output / Limits → Cycle time. Set CycleTime = 0.3 s. The block will be called every 100 ms (its OB cycle) and update the output every third call.
6. Wire I/O. In each PID's configuration, set Input to the PT100 scaled value (e.g. "DB_Zone1".ProcessValue), Input_PER to the raw RTD word (e.g. %IW0), and OutputHeat to the scaled AO word (e.g. "DB_Zone1".Output).
7. Compile and download. Compile the project (Hardware and Software), then download to the CPU. Use "Download to target device" with PG/PC interface = PROFINET.
8. Perform CPU online diagnostics. Right-click the CPU → Online & diagnostics → Cycle time. Confirm OB1, OB30, OB31, OB32, OB33, OB34 cycle times are within tolerance.

10. Cycle-Time Budget & Watchdog Analysis

Compute the worst-case execution time of each cyclic OB to confirm the watchdog is not violated.

OB30 worst-case (5 x PID_Temp, 1512SP DK02):
  1x PID_Temp execution time, typ.   1.2 ms
  5x =                              6.0 ms
  + 7x RTD input scan (overlapped)   0.4 ms
  + 7x AO write (overlapped)        0.2 ms
  + alarm generation + HMI update    0.4 ms
  -----------------------------------------
  Total OB30 execution              7.0 ms
  Cycle time                        100 ms
  Headroom                          93 ms (approx. 15x)

For the 1214C, the same loop computes to:

OB30 worst-case (5 x PID_Compact, 1214C):
  1x PID_Compact execution time     2.0 ms
  5x =                              10.0 ms
  + I/O scan (local modules)         3.0 ms
  + supervisory calls                2.0 ms
  -----------------------------------------
  Total OB30 execution             15.0 ms
  Cycle time                       100 ms
  Headroom                         85 ms (approx. 6.7x)

Both controllers clear the watchdog. The 1214C is operating with only 6.7× margin; if the user adds a second HMI poll, a GRAPH sequence, or a safety program, the margin tightens below 5× and the PID sample time becomes fragile. Field experience on earlier 1512SP hardware (FW 2.0, 16 PID_Compact loops + 100 ms safety program + 2–3 GRAPH blocks) was that the 100 ms cycle time had to be relaxed to 200 ms. On the DK02 hardware, the 25 PIDs at 300 ms cycle is comfortable.

11. Online Diagnostics & Acceptance Test

A repeatable acceptance test confirms the design before hand-over:

1. Cycle-time trace. Open the Online & diagnostics view → Cycle time. Record OB1, OB30, OB31, OB32, OB33, OB34 minimum, average, and maximum cycle times over 5 minutes. The maximum should be below 50% of the cycle time on both CPUs.
2. Memory utilisation. Online & diagnostics → Memory. Confirm used work memory is below 70% of the available 200 KB (1512SP) or 70% of 100 KB (1214C, with PID_Compact).
3. Step-response test. On one zone, set a +20 °C setpoint step from ambient. Record the process value, the controller output, and the manipulated variable in the trace. The controlled temperature should reach the new setpoint without overshoot larger than 2 °C and without sustained oscillation. Use this zone to tune Gain, Ti, Td manually if autotune is unsatisfactory.
4. Disturbance-rejection test. Open a door / disturb the airflow for 10 s on the same zone. The PID should re-converge to setpoint within 2 minutes with no oscillation. Document the IAE (Integral of Absolute Error).
5. Wire-break test. Disconnect one PT100 lead. The PID should drop its output to a configurable safe value (default 0%) within 1 cycle and raise a wire-break alarm. Reconnect the lead and confirm automatic recovery.
6. Watchdog test. Briefly insert a delay loop (e.g. 50 ms busy-wait) in OB30 and download. The OB should time-out, the CPU should enter STOP, and the diagnostic buffer should record "OB30 time-out". Remove the test loop and restart.

If any step fails (cycle time > 50%, memory > 70%, step response overshoots > 5 °C), revisit the cyclic OB count or move from PID_Compact on a 1214C to PID_Temp on a 1512SP. Do not raise the cycle time above 300 ms without re-checking the process dynamics: thermal mass time constants are usually long, but the disturbance spectrum from a multi-zone system can be much faster than the τ of a single zone.

Decision Summary

12. Frequently Asked Questions