The PLC counter shows no dependable pulse count even though the two-pin Hall sensor changes state. The sensor produces about 7.7–8.8 VDC in its low state and 11.3–12.7 VDC in its high state, while the 6ES7138-6AA01-0BA0 card expects 24 VDC pulses. Start here: treat the problem as level discrimination followed by output conversion. A passive divider only scales the two voltages; it does not create a reliable switching threshold between them.
Measure the two states at the connected sensor
Measure at the point where the interface will connect, with the Hall sensor powered from 13 VDC and operating at its real switching speed. Use an oscilloscope when possible; a meter can hide short pulses, edge noise, and voltage sag.
- Measure the low-state minimum and maximum relative to the sensor return.
- Measure the high-state minimum and maximum at the same point.
- Capture pulse width, repetition rate, rise time, fall time, overshoot, and any noise near the transition.
- Repeat the measurements with the proposed interface attached. Loading must not move the states out of their recorded ranges.
The stated ranges leave a guaranteed discrimination band from 8.8 V, the highest low state, to 11.3 V, the lowest high state. That band is 2.5 V wide. If the measured ranges overlap in the machine, fix the sensor supply, wiring, grounding, or load before building a converter.
Clarify what the specified 182 Ω resistance represents. Do not use it as an external shunt value unless the sensor documentation identifies it that way. If 182 Ω were connected directly across 13 VDC, it would draw approximately 13 V / 182 Ω = 71 mA and dissipate 13² / 182 Ω = 0.93 W; that load could materially change the signal.
Put the switching thresholds inside the gap
Use a comparator or threshold input with hysteresis. A practical nominal center is about 10.05 V, the midpoint between 8.8 V and 11.3 V. The final thresholds must include reference accuracy, resistor tolerance, temperature drift, input bias, sensor variation, and measured noise.
One design target is a rising threshold of 10.5 V and a falling threshold of 9.5 V. Those assumed targets leave 0.8 V between the minimum high state and the rising threshold, and 0.7 V between the maximum low state and the falling threshold. Recalculate the worst-case thresholds with component tolerances before releasing the circuit.
Hysteresis matters because a single threshold can chatter when a slow or noisy edge crosses it. The rising threshold asserts the output; the lower falling threshold releases it. Keep both thresholds above 8.8 V and below 11.3 V under all stated tolerances.
Choose isolation before selecting the output stage
Use an isolated interface when the sensor and PLC supplies cannot share a reference, when ground-potential differences are expected, or when the field wiring needs a galvanic barrier. On the sensor side, let the comparator make the voltage decision and then drive the optocoupler. On the PLC side, power the output from the appropriate 24 VDC field supply.
If isolation is unnecessary, use the same threshold stage followed by a transistor output. First read the card wiring diagram and determine whether its channel requires a sourcing or sinking field signal. Match its published on-state voltage, off-state voltage, input current, minimum pulse width, maximum count frequency, and input filter settings. That is not the fault to guess at: a correctly detected Hall transition still will not count if the output polarity or pulse width is wrong.
Reject fixes that only move the voltage
| Reading or symptom | Cause and next action |
|---|---|
| Both divided voltages remain on the same side of the receiver threshold | A divider changes amplitude but provides no decision function. Add a comparator with hysteresis. |
| The interface changes state several times per Hall transition | Noise or a slow edge is crossing a threshold repeatedly. Add calculated hysteresis and inspect grounding and routing. |
| The comparator changes cleanly but the PLC count does not | Check output polarity, field common, card thresholds, channel configuration, filter time, and minimum accepted pulse width. |
| The Hall voltages change after connecting the interface | The interface is loading the two-wire circuit. Raise its input impedance or use a suitable buffer. |
| The count becomes unreliable only at higher speed | Measure the actual pulse width and frequency, then compare them with the card settings and documented limits. |
A divider is valid only when all three inequalities hold for its scale factor k: k × 8.8 V < VIL(max), k × 11.3 V > VIH(min), and k × 12.7 V remains within the receiver rating. Obtain VIL(max), VIH(min), and the absolute input limit from the receiving device documentation. Without those values, selecting the divider is blind.
A 7.5 V Zener level shift does not by itself define a clean threshold. Ideal subtraction produces 0.2–1.3 V for the stated low range and 3.8–5.2 V for the high range, before Zener tolerance, dynamic-current behavior, series-resistor drop, and optocoupler input voltage are included. Compare the full ranges with the guaranteed input specifications of the proposed 0–5 V device, including PXC.2964270. Do the same threshold analysis for the proposed 0–10 V device MURR.6652500; its nominal range alone does not prove that it will switch between 8.8 V and 11.3 V.
Build the resolving signal path
- Feed the Hall signal into a high-impedance comparator input so the two-wire sensor remains within its measured state ranges.
- Create a stable reference and resistor network that place the rising and falling thresholds inside the 8.8–11.3 V gap after worst-case tolerances.
- Add hysteresis around the comparator. Confirm both thresholds by slowly sweeping the input voltage and recording the two switching points.
- Drive an optocoupler for an isolated design, or a transistor for a shared-reference design. Select its series and pull-up components from the devices’ documented currents and ratings.
- Configure the output side to present the polarity and 24 VDC levels required by the
6ES7138-6AA01-0BA0channel. - Set the PLC channel mode and input filtering from the card documentation and the measured pulse width and frequency.
Do not connect the Hall signal directly to the 24 VDC pulse input unless the card documentation explicitly accepts both recorded Hall levels as distinct low and high states. Do not apply the PLC field voltage to the sensor-side signal node.
Verify every boundary, not just one pulse
- Apply 7.7 V through 8.8 V to the interface input and verify that every value produces the inactive PLC state.
- Apply 11.3 V through 12.7 V and verify that every value produces the active PLC state.
- Sweep upward and downward through the gap. Record the actual rising and falling thresholds and compare them with the tolerance calculation.
- Run the Hall sensor at minimum and maximum machine speed. Compare oscilloscope edge counts at the sensor, interface output, and PLC counter over the same observation interval.
- Interrupt the sensor supply, disconnect the signal, and restore power. Confirm that no unintended count occurs during startup, shutdown, or an open circuit.
If the sensor-side transitions match the PLC input transitions but the count differs, inspect the channel diagnostic information and configuration rather than changing the analog threshold circuit. If the discrepancy begins at a specific speed, capture the narrowest pulse at that speed and compare it directly with the configured filter and the card’s documented pulse requirements.
FAQ
How do I choose the Hall sensor switching voltage?
Place the rising and falling thresholds inside the guaranteed 8.8–11.3 V gap. Nominal targets of 10.5 V rising and 9.5 V falling are workable only after component tolerance, drift, loading, and measured noise are included.
How do I convert the Hall signal to a 24 V PLC pulse?
Use a comparator with hysteresis to detect the Hall state, then drive an isolated or non-isolated transistor output from the PLC-side 24 VDC supply. Match the output polarity and electrical limits to the 6ES7138-6AA01-0BA0 documentation.
How do I prove the PLC is missing pulses?
Count the same transitions simultaneously at the Hall signal, interface output, and PLC counter. Measure the narrowest pulse and compare it with the channel filter setting and the card’s documented minimum pulse requirements.
Stop and escalate to Siemens official support when the electrical waveform at the card terminals meets the documented levels and pulse requirements but 6ES7138-6AA01-0BA0 still miscounts or reports unexplained diagnostics. Provide the channel configuration, wiring diagram, supply measurements, oscilloscope captures, measured pulse rate and width, and diagnostic records.