Multiple CLR Outputs on One Rung: MicroLogix 1200 RSLogix 500

Problem Overview

On a MicroLogix 1200 (Series C) controller programmed with RSLogix 500, an attempt to place more than one CLR (Clear) instruction in series on the right-hand side of a single ladder rung fails verification with the error:

Rung 2 Ins 3: ERROR: Invalid Output instruction position!

The first CLR shifts to the left side of the rung the moment a second CLR is inserted, which indicates the editor is treating the second clear as an input-style condition rather than an output action. This is a structural restriction of the RSLogix 500/IEC-1131 ladder editor, not a controller fault.

Affected Products and Versions

Root Cause: RSLogix 500 Output-Rung Architecture

RSLogix 500 follows the classic AB ladder diagram convention:

1. A rung is evaluated left-to-right; power flow begins at the left rail.
2. The last instruction on the right side of the rung is the canonical output instruction. Only one such instruction can occupy the terminal position.
3. All other output instructions (OTE, OTL, OTU, RES, CLR, etc.) must be placed in parallel branches that terminate together at the right rail.

Placing CLR in series as CLR B3:0 → CLR B3:1 → CLR B3:2 violates rule 2; the second and third instructions cannot be anchored at the output position, so the editor promotes the trailing CLR to the left rail and the verify phase rejects the rung with error 0xE03E / "Invalid Output instruction position".

Three Valid Solutions

Solution 1 — Parallel Branch (BST / NXB / BND)

Use nested branches so all three CLR outputs share the same input condition and sit in parallel at the output side of the rung.

|  XIC S:1/15      BST          CLR B3:0  |
|                 |--- CLR B3:1  NXB  ---  |
|                 |--- CLR B3:2  BND       |

Execution model: when the input condition (S:1/15, First Pass bit) is true, all three branches are evaluated and all three words are cleared in the same scan.

Solution 2 — File Fill (FLL) Instruction

The FLL instruction fills a contiguous block of words with a single source value. It is the most compact method to clear a range of binary words.

|  XIC S:1/15                FLL       |
|                          Source: 0    |
|                         Dest: #B3:0   |
|                         Length: 3    |

Solution 3 — Multiple Rungs, Same Condition

Three rungs with identical input conditions, each containing a single CLR. Functionally correct, but it inflates scan time, program word count, and ladder complexity. Use only when the branches must clear non-contiguous addresses and FLL is unsuitable.

Solution Comparison

Performance note: FLL with three words takes roughly 2.3× longer than three individual CLR instructions because of the file-mode addressing overhead. For a MicroLogix 1200 with a typical 1–2 ms scan this is invisible; on a 1000-word bulk clear, FLL wins decisively because the constant overhead is amortized.

Step-by-Step: Implementing the FLL Method on MicroLogix 1200

1. Open the RSLogix 500 project for the ML1200 Series C.
2. Navigate to the program file (e.g. MAIN, ladder routine Routine_001).
3. Insert a new rung. Place the input condition (e.g. XIC S:1/15 for First Pass, or a real input such as XIC I:0/0).
4. From the File / Bit instruction toolbar or the Instruction Browser, select FLL.
5. Drop the FLL block in the output position (the rightmost grid square of the rung).
6. Double-click the Source field; enter 0.
7. Double-click the Destination field; enter #B3:0. The leading # is required.
8. Double-click the Length field; enter the number of 16-bit words to clear (e.g. 3 for B3:0, B3:1, B3:2).
9. Press F8 (or Verify Project) to confirm the rung validates without warnings.
10. Download to the controller and switch to Run mode.

Step-by-Step: Implementing the Parallel-Branch Method

1. Insert the input condition at the left rail (e.g. XIC S:1/15).
2. From the Branch toolbar, click BST to start a parallel branch; place it directly to the right of the input condition.
3. Drop CLR B3:0 in the lower output grid of the BST branch.
4. Click NXB to add the next branch; drop CLR B3:1 in the lower grid of this branch.
5. Click NXB again; drop CLR B3:2.
6. Click BND to terminate the branches and tie them to the right rail.
7. Verify with F8. All three CLRs should sit visually stacked in parallel, not in series.

CLR vs. FLL — Instruction Semantics

Common Mistakes and Error Recovery

Verification Procedure

1. In RSLogix 500, select Project → Verify Project (or press F8). The error "Invalid Output instruction position" must no longer appear.
2. Open the Data File window, select B3, and watch the values of B3:0, B3:1, B3:2 in run mode.
3. Force the input condition true (or rely on First Pass S:1/15).
4. Confirm B3:0, B3:1, B3:2 all read 0000 0000 0000 0000 after the qualifying event.
5. Toggle the condition false; the values should remain at zero (CLR is non-retentive in the sense that it does not re-trigger, but it is also not latched — a subsequent logic path can set bits again).
6. Check the controller's Scan Time window; the chosen method should not increase the periodic scan time beyond project budget.

Scan-Time and Memory Considerations

On a MicroLogix 1200 Series C, the periodic scan is typically 1–3 ms for a small program. The execution-time difference between three CLR instructions and one FLL of length 3 is sub-microsecond relative to that scan; it is rarely a deciding factor for three words. The choice should be driven by:

• Number of targets — FLL scales linearly with one constant overhead; CLRs scale linearly per word. FLL becomes faster at ≈ 4+ contiguous words.
• Code clarity — CLR with named addresses (e.g. CLR Fault_Word_1) is more self-documenting than FLL Source:0 Dest:#B3:5 Length:10.
• Memory map — FLL will happily overrun if the destination file boundary is crossed. CLR is inherently bounded to its single operand.

Branch Instruction Reference

Branches can be nested; each BST requires a matching BND, and each NXB adds an additional parallel path within the current branch group. This is the only RSLogix 500 construct that legally places multiple output instructions in a single rung.

RSLogix 500 vs. RSLogix 5000 / Studio 5000

RSLogix 5000 (and its successor, Studio 5000 Logix Designer for ControlLogix/CompactLogix) removed the single-output-per-rung restriction. Outputs can be chained in series because the tag-based execution model evaluates each instruction independently. If your project is being migrated to a CompactLogix or ControlLogix platform, the same logic can be written simply as CLR tagA; CLR tagB; CLR tagC; in a single rung without branches. This is one of the most common behavioural differences encountered during ML1200-to-CompactLogix conversions.

FAQ