An NI FPGA-to-host DMA FIFO requires storage on both sides of the transfer. Host RAM can retain a large data set, but it does not replace the FPGA-side queue that accepts producer data before DMA moves it to the host. The evidence does not establish a universal maximum transfer rate; measure that rate on the actual target and host.
Separate finite capture from continuous streaming
The source describes both the limited and “unlimited” cases as n<100,000, so the intended distinction is ambiguous. Treat them as separate engineering cases: a finite acquisition has a defined sample count, while continuous streaming has no predetermined endpoint.
| Case | Acceptance condition | Primary risk |
|---|---|---|
| Finite capture | All generated elements reach the host without FIFO overflow. | A temporary producer-consumer mismatch exceeds available buffering. |
| Continuous streaming | The sustained host drain rate is at least the sustained FPGA production rate. | Any persistent rate deficit eventually fills every finite FIFO. |
Determine the maximum rate by measurement
No maximum rate can be calculated from the evidence because it does not provide element width, DMA-interface capacity, bus loading, host read-loop throughput, or timing measurements. Determine the usable rate by increasing the FPGA production rate while monitoring transferred element counts, FIFO occupancy or overflow indication, and host-side continuity.
Continuous operation: R_host >= R_fpga
FIFO occupancy change: DeltaQ = (R_fpga - R_host) * DeltaT
Finite capture requirement: Q_available >= maximum accumulated DeltaQThese symbolic relationships do not assign an undocumented hardware limit. If R_fpga remains greater than R_host, a deeper FIFO only delays overflow; it cannot make the stream sustainable.
Choose FPGA-side FIFO depth
The FPGA-side FIFO buffers data when the timed producer and host-side consumer do not run in lockstep. Increasing its depth provides more tolerance for temporary host or transfer delays and permits a larger burst to accumulate before overflow. It does not increase the long-term end-to-end rate when the host drains data more slowly than the FPGA produces it.
For host transfer, the evidence identifies FPGA RAM as the applicable FIFO storage. LUT and flip-flop storage are described as target-scoped and therefore not usable for transfer to the host. A front-panel element can carry a small amount of unbuffered data, but it requires polling rather than providing the buffered DMA path used for larger acquisitions.
Verify the 7831 configuration
- Start with the reported configuration: a 20 MHz timed loop producing data at 20 MHz, an FPGA FIFO depth of 15 elements, and a host allocation of 100M elements.
- Run for the required acquisition duration and compare the number of elements generated, transferred, and consumed.
- Check whether FPGA FIFO occupancy reaches its limit or an overflow is reported. If it does, increase FPGA depth only after confirming that the deficit is temporary.
- Extend the test beyond the reported several-second run. Stable short-run transfer does not establish unlimited continuous operation.
The reported configuration transferred data continuously for several seconds without an observed problem. That result validates only the tested duration and data definition; it does not prove a universal 20 MHz DMA limit or indefinite operation.
FAQ
Does a 100M-element host FIFO eliminate the FPGA FIFO?
No. Host RAM retains data after transfer, while the FPGA FIFO buffers producer data before DMA delivers it to the host.
Will increasing the FPGA DMA FIFO depth raise the continuous transfer rate?
Not by itself. More depth absorbs temporary rate mismatches, but continuous operation still requires the sustained host drain rate to meet or exceed the FPGA production rate.
Does the 20 MHz test prove that the NI 7831 can stream indefinitely?
No. The evidence reports successful transfer for several seconds using a 15-element FPGA FIFO and a 100M-element host allocation; verify a longer run and monitor counts and overflow before treating it as continuous.