Omron CPM1A Quick Response Inputs: DM6628 Configuration Reference

James Nishida13 min read
CJ/CP SeriesOmronTechnical Reference
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Omron CPM1A Quick Response Inputs and I/O Addressing Reference

The Omron CPM1A is the entry-level fixed-I/O controller in the CP-family lineage and the most common platform used by engineers transitioning from smart relays to true PLCs. It supports online program editing, ladder logic with full BCD/binary literal support, and a flexible memory map that scales into the CJ1 and CS1 architectures. One of its most underused features is the quick response input block, which captures pulses shorter than one scan cycle by latching them in a hardware register until the next I/O refresh.

This reference consolidates the CPM1A memory map, I/O channel allocation rules, DM6628 quick-response configuration, and the supporting CX-Programmer workflow. It is written for first-time CP-family users who need to capture sub-scan pulses (e.g. a magnetic reed switch on a short-travel pneumatic cylinder) without resorting to interrupt task programming.

CX-Programmer scope: CX-Programmer version 4.0x (also referenced historically as 4.01) is the engineering environment for the CPM1A, CPM2A/CPM2C, CQM1H, SRM1, CJ1, CS1, and CP1 series. The same project tree structure and DM/IR/CIO/TIM/ CNT/TIMH memory model is used across the entire CP/CJ/CS family, so the addressing conventions described below scale to larger controllers without modification.

1. CPM1A Memory Architecture Overview

The CPM1A organises all memory into numbered channels. Each channel holds 16 bits addressed as channel.bit (for example, IR000.06 or 200.07). Three address families matter most for I/O and pulse handling:

Area Prefix CPM1A Range Purpose
I/O / Internal Relay (IR) IR (or no prefix) IR000–IR009 (physical I/O), IR010–IR231 (work relays) Bit I/O, internal markers, work area
Data Memory (DM) DM DM0000–DM2043, DM6144–DM6599 (read-only setup), DM6600–DM6655 (setup) 16-bit word storage, PLC setup parameters
Timer/Counter TIM/CNT TIM/CNT 000–127 100 ms timers, counters, TIMH (10 ms)
Holding Relay (HR) HR HR00–HR19 Retained bit storage (battery-backed)
Auxiliary Relay (AR) AR AR00–AR15 System flags, retained

The fixed-I/O CPM1A-CPU has hard-wired terminal-to-IR mappings. For example, a 20-point CPU exposes inputs IR000.00 through IR000.11 and outputs IR010.00 through IR011.07. Expansion I/O modules, when used, continue the IR range contiguously based on the rack position. There is no rack/slot/%I/%Q prefix in CX-Programmer – engineers simply type the numeric address and the editor resolves it.

2. I/O Channel Allocation Rules (CJ1/CS1 Scaling)

Although the CPM1A has fixed I/O, the same allocation logic is used by the larger CJ1 and CS1 PLCs, where plug-in I/O cards can be remapped to any starting channel. Understanding the rule now prevents confusion when the user later migrates to modular hardware.

2.1 Bit-width per card

Card type Bit width Channels consumed
16-point input / output 16 bits 1 channel
32-point input / output 32 bits 2 contiguous channels
64-point input / output 64 bits 4 contiguous channels
Analogue input (typical) 10 contiguous channels (e.g. 2000–2009)

2.2 Allocation example (CJ1 rack starting at channel 0)

Slot Card Channel range Bit range
1 16-point input 00000 00000.00–00000.15
2 32-point output 00001–00002 00001.00–00002.15
3 64-point input 00003–00006 00003.00–00006.15
4 Analogue input 00200–00209 (10 ch) n/a (word data)

To address bit 10 of the third card's first channel (i.e. IR00003.10), type 310 into a contact in CX-Programmer. The editor interprets the value as channel.bit by splitting 310 into channel 31 and bit 0; for a 64-point card the same numeric shorthand continues into subsequent channels. For larger controllers the rack number itself becomes the first digit, so 0310 means rack 0, channel 310.

3. BCD and Binary Literals in CX-Programmer

CX-Programmer distinguishes literal number bases with a prefix character on the constant value:

Prefix Base Example Meaning
# BCD > D2010 #37 Compare DM2010 to decimal 37, encoded BCD
& Binary (hex on display, decimal entry) &100 Decimal 256 (used for binary-tagged operands)
(no prefix) Decimal 100 Plain decimal 100

The compare ladder instruction > with operands D2010 (DM word) and #37 (BCD literal) evaluates true when DM2010 contains the BCD-encoded value 37. Mismatched bases will silently fail at the next BCD instruction in the chain, so always match the prefix to the source word's encoding.

4. Quick Response Inputs: Functional Principle

Every CPU scan consists of four phases: I/O refresh → program execution → housekeeping → end-of-task. A pulse shorter than one scan time may arrive and depart entirely between two refreshes, so the program never sees the rising edge. Quick response inputs solve this by hardware-latching the pulse in a flip-flop that is independent of scan timing.

Reed / Sensor pulse width < scan time Hardware latch set on rising edge IR bit IR00003..06 Latch cleared at next I/O refresh Pulse IR bit (latched through scan)

The latch holds the bit high until the next I/O refresh at end-of-scan, at which point it is cleared. This guarantees that the program sees the rising edge on the next execution pass. Important constraints:

  • The mechanism is a pulse stretcher, not a true high-speed counter. It does not speed up program execution – it merely guarantees that a sub-scan pulse is captured.
  • It is intended for single short pulses, not trains of pulses faster than the scan rate.
  • If the requirement is counting pulse frequency or quadrature, use the dedicated high-speed counter inputs and a CTBL/INI/HSCR instruction set instead.

5. CPM1A Quick Response Input Allocations

On the CPM1A, quick response capability is reserved for IR00003 through IR00006. That is, only bits IR000.03, IR000.04, IR000.05, and IR000.06 are hardware-eligible. Each of these four points is mapped to the corresponding physical input terminal on the CPU; the CPM1A's fixed input mapping means you do not have to assign which terminal is fast – the mapping is fixed by hardware.

Quick response input CPU terminal (20-pt example) PLC Setup word Bit position in word
IR000.03 Input 03 DM6628 bit 03
IR000.04 Input 04 DM6628 bit 04
IR000.05 Input 05 DM6628 bit 05
IR000.06 Input 06 DM6628 bit 06
IR000.00–IR000.02 do not support quick response. They use the normal input filter, defaulting to 8 ms (DM6620). On the CQM1H the equivalent settings live in DM6628 as well, but additional quick-response-capable bits exist on the CQM1H's interrupt inputs (IN0–IN3). Always verify the exact CPU part number before assuming the bit range.

6. DM6628 Configuration Procedure

DM6628 is a 16-bit Setup Area word that enables quick response and interrupt inputs. By default, after a power-on memory clear, every bit is 0, meaning the four inputs run in standard filtered mode.

6.1 Bit map of DM6628 (CPM1A)

Bit Function when set to 1
00–02 Reserved (always 0)
03 IR000.03 quick response enable
04 IR000.04 quick response enable
05 IR000.05 quick response enable
06 IR000.06 quick response enable
07–14 Reserved / interrupt-related (see manual)
15 Reserved (always 0)

6.2 Step-by-step CX-Programmer procedure

  1. Connect to the PLC in Online mode. The DM area setup words (DM6600–DM6655) are read/write only while online or after a Stop-mode transfer; offline they cannot be edited in the PLC.
  2. In the project tree, expand PLCSetupPLC Setup. CX-Programmer displays the setup table editor.
  3. Navigate to address DM6628. The default value displayed is 0000 (all bits zero).
  4. To enable quick response on IR000.06 only, write the literal 0010 0000 0000 0000 (binary), which is #1000 BCD or &64 decimal in CX-Programmer notation (the constant #64 or &64 turns bit 06 on).
  5. To enable IR000.05 and IR000.06 together, write 0001 1000 0000 0000 binary → bits 05 and 06 set. The decimal value is 96; in BCD notation #96; in binary notation &96.
  6. Click Transfer to PLC. The PLC must be in Program (Stop) mode for Setup Area writes from CX-Programmer – some firmware revisions also permit Monitor-mode writes with confirmation.
  7. Switch back to Run or Monitor mode and verify the value persisted by reading DM6628 back from the CPU.

6.3 Verification ladder (optional diagnostic)

|  IR000.06       OUT     200.07
|  |--||----------( )-----|  (captured pulse indicator)
|
|  TIM0001    #5
|  |--(T)------------------ (5 s auto-clear of indicator)

Latch bit 200.07 when the quick-response input fires, then auto-reset via a 100 ms × 5 TIM to keep the indicator on long enough for a human to see.

7. Input Constant Filter (DM6620)

DM6620 controls the 8 ms hardware filter applied to inputs that are not in quick-response mode. For inputs 0–7 of IR000, bits 00–07 select the input; setting the corresponding bit to 1 forces a 1 ms filter instead of 8 ms. For quick-response inputs this filter is bypassed – the hardware latch responds to the bare electrical edge.

DM6620 bit Affects Value 0 Value 1
00–07 IR000.00–IR000.07 filter time 8 ms default 1 ms fast filter
08–15 Reserved / CPU variant dependent
Setting rule: the input filter constant must be longer than the scan time, never shorter. If you lower the filter to 1 ms but the scan is 5 ms, a single 1 ms pulse may still be missed because the CPU samples inputs only at I/O refresh. For sub-scan pulses on filtered inputs, always enable quick response rather than lowering the filter.

8. Interrupt Inputs vs Quick Response Inputs

Both feature sets share DM6628 but serve different purposes. Choose correctly or you will lose the timing guarantee you are trying to achieve.

Feature Quick response Interrupt input
Edge captured? Yes (rising edge) Yes (rising or falling)
Sub-scan capture? Yes (via hardware latch) Yes (via hardware interrupt)
Response latency One full scan (after next I/O refresh) < 1 ms (interrupt task pre-empts scan)
Use case Detect brief pulse, act on it in normal scan Execute critical code immediately on edge
Program impact None – standard ladder Requires INT task (e.g. INT 0..3) plus MSKS instruction
Configure via DM6628 bits 03–06 DM6628 bits 07+ and INI/MSKS

9. Application: Robotic Arm Retract on Plastic Injection Moulder

A common real-world use case is signalling the IMM (Injection Moulding Machine) to close its mould the moment the take-out robot's 1.5 m arm finishes its outward travel. A magnetic reed switch at full extension fires briefly; if the closing signal is generated only after the next scan, the IMM cycle is delayed by one scan period (typically 5–15 ms). With quick response, the bit is reliable; with interrupt, the mould-close contactor can fire sub-millisecond from the edge.

9.1 Ladder example (CX-Programmer)

Step 0001   IR000.06         TIM0001        #3
           |--||-------------( T )-----------|  (300 ms debounce after quick-response latch clears)

Step 0002   TIM0001         OUT  010.00
           |--||------------( )--------------|  (close-mould output to IMM)

Step 0003   IR000.06         OUT  HR00.00
           |--||------------( )--------------|  (retained event log bit)

DM6628 should contain #64 (bit 06 set) before commissioning. Verify by forcing IR000.06 with a screwdriver on the input terminal and watching HR00.00 latch.

10. Online Programming: Why It Matters for the CPM1A

The CPM1A supports online editing while the PLC is in Monitor mode – you can modify contacts, coils, and TIM/CNT preset values without stopping the controller. Edits are buffered and applied at end-of-task. This single feature is often the differentiator when selecting a micro-PLC:

Brand / model Online program edit Function-key workflow Note
Omron CPM1A / CP1L Yes Yes (F2 = NO contact default) Recommended entry point
Omron Zen Front-panel only n/a Smart relay, expandable up to 60 I/O
Schneider Zelio No (ladder via software only) n/a Limited online diagnostics
Schneider Twido No native online edit n/a Stop required to download
AB MicroLogix Limited Yes RSLogix 500 workflow
Moeller Easy Front-panel circuit editor n/a Smart relay

Online editing eliminates the download/restart cycle that lengthens commissioning. For a CPM1A retro-fit on a running machine, this is often the only way to tune TIM presets without shutting down the line.

11. CX-Programmer Productivity Shortcuts

Beyond quick response, CX-Programmer's keyboard-driven workflow is one of the fastest in any PLC IDE. Recommended mappings (Tools → Options → Keyboard Mapping):

Key Default function Suggested bind
F2 Normally-open contact — (already mapped)
F3 Normally-closed contact
F4 Output coil
F5 Compare instruction
F8 Function block Set as TIM/CNT preset dialog
Ctrl+B Bookmark rung

Pressing F2 then typing 6 inserts IR000.06 as a contact. The numeric shorthand is the same one used in addressing on the CJ1/CS1 platforms, so muscle memory transfers between controllers.

12. Troubleshooting Matrix

Symptom Likely root cause Verification Fix
Brief pulse never latches in IR Input is not in IR00003–IR00006, or DM6628 bit not set Read DM6628 online; check terminal mapping Re-wire to a quick-response-capable terminal, or write the DM6628 bit, or use interrupt input
IR bit sticks ON after pulse Latch not cleared because PLC in Stop Verify PLC mode (Run/Monitor vs Program) Switch to Run/Monitor; verify ladder references the bit and clears it via DIFU/DIFD or contact
Pulse counted twice Using filtered and quick-response input together; signal bounce Scope the input; check DM6620 bits Add hardware debounce; clear DM6620 fast-filter bits
DM6628 write rejected PLC in Run mode, firmware locks setup Check CX-Programmer transfer result Switch to Program/Monitor and retry
Bit 05 and 06 behave identically Both DM6628 bits set unintentionally Read DM6628 back Clear bit 05 to 0 if only bit 06 is required
Scan time longer than pulse Misunderstanding of quick response Read scan time in CX-Programmer status bar Use interrupt task if sub-scan latency is required, not just sub-scan capture

13. Field Commissioning Checklist

  1. Document the target scan time before connecting any quick-response input. CX-Programmer displays it in the status bar of an online connection.
  2. Confirm DM6620 filter bits are at default (0) for inputs that will use quick response.
  3. Write DM6628 with the desired bit pattern while the PLC is in Program mode.
  4. From a known clean state, force the input with a test pulse generator and confirm the corresponding IR bit sets.
  5. Verify the latch clears on the next I/O refresh by watching the bit transition back to 0 within one scan.
  6. Back up the Setup Area to disk via PLC → Transfer → From PLC so the values can be restored on a memory clear.
Backup reminder: DM6600–DM6655 revert to default after a memory clear. The project file must include an export of the Setup Area or commissioning requires re-entering every value by hand.

14. Document References

  • Omron CPM1A Operation Manual (Cat. No. W451) – memory map and DM Setup Area definitions.
  • Omron CX-Programmer Operation Manual (Cat. No. W446) – Setup editor, online transfer, keyboard mapping.
  • Omron CX-One / CX-Programmer Version 4.x Setup Manual – installation, USB serial converter notes, controller-link configuration.
  • Omron CP1L Operation Manual (Cat. No. W462) – successor platform with extended quick-response and interrupt input ranges.

All manuals are available from the Omron Industrial Automation website (ia.omron.com) and the regional support portal. Always verify the manual revision matches the CPU's lot/serial number suffix before applying DM6628 settings.

What is DM6628 used for on the CPM1A?

DM6628 enables quick response inputs on IR000.03 through IR000.06 and configures interrupt input behaviour. Set bit 03–06 to 1 to enable quick-response hardware latching on the corresponding input. Default value is 0 (filtered input).

Can IR000.00 capture a sub-scan pulse?

No. Only IR000.03–IR000.06 on the CPM1A support quick-response hardware latching. IR000.00–IR000.02 are filtered through DM6620 (8 ms default). If a sub-scan pulse must be captured on input 00, re-wire the signal to input 03–06 and enable the corresponding DM6628 bit.

Why does my quick-response bit stay ON after the pulse ends?

The hardware latch is supposed to clear at the next I/O refresh. If it appears stuck, the PLC is likely in Program (Stop) mode, the rung never reads the bit to clear it, or you are observing the bit in the Setup dialog rather than during Monitor mode. Verify PLC mode is Run or Monitor and that the ladder includes the bit in its scan path.

Should I use quick response or an interrupt task?

Use quick response when you need to detect a short pulse and react to it in normal scan within one cycle. Use an interrupt task (with MSKS/INI) when you need to act on the edge within sub-millisecond latency or run a specific task independent of scan. Quick response captures the edge; interrupts pre-empt the scan.

Does changing DM6628 require the PLC to be stopped?

Most CPM1A firmware revisions permit Setup Area (DM6600–DM6655) writes only while the PLC is in Program (Stop) mode. Some recent firmware builds allow Monitor-mode writes with an on-screen confirmation. If the transfer fails, switch to Stop, write the value, verify with a read, then return to Run.

How can I confirm the input filter is not masking my pulse?

Read DM6620 online. The default value is 0 (8 ms filter) for inputs 00–07. Set the relevant bit to 0 explicitly (not to 1) so the 8 ms filter is in effect; for quick-response inputs this filter is bypassed entirely. Always set the filter time longer than the scan, never shorter.

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