After correcting the gate connections and confirming that no MOSFET was damaged, an unloaded high-voltage output may still measure 24 V. That reading is the normal pull-up state of this interface, not proof that the 24 V rail is shorted to an unrelated trace.
Voltage, current, and gate stress
The number that matters is not voltage alone. A high-impedance meter draws very little current, so even a weak pull-up can charge an open trace to the full 24 V rail. Measure the node under its intended load and measure current through the signal path before classifying the reading as leakage, coupling, or a short.
Heating follows current and resistance: P = V × I and P = I²R. An open node can sit at 24 V while dissipating almost no load power. This is why an unloaded voltage reading may look alarming without producing meaningful thermal load.
The gate connection creates a separate electrical limit. The implemented circuit tied the MOSFET gates to the input and output rather than to the low-voltage and high-voltage supplies shown by the application circuit. That error can place 24 V from gate to source on the high-voltage MOSFET. Its stated maximum is 20 V, so the device can be overstressed even if the board initially appears to switch.
| Quantity | Limit or expected state | Where to read or measure it |
|---|---|---|
| High-side open-circuit voltage | 24 V is expected when the node is pulled up and neither side pulls low | Measure output to its high-side reference |
| Low-side logic supply | 3.3 V | Measure at the board supply and logic-side pull-up |
| High-side supply | 24 V | Measure at the board supply and high-side pull-up |
High-side MOSFET VGS
|
Must remain within the stated 20 V maximum | Measure gate directly to source, including during power-up and switching |
| PLC input current | Entire input current must be handled by the low-pulling path | Read the PLC input specification and measure the loaded channel current |
| PLC output low level | Must be below the Raspberry Pi input-low threshold | Measure at the Pi input under load and compare with its electrical specification |
Expected pull-up versus electrical fault
In the correctly connected level-shifter circuit, leaving either signal side open represents logic high. With the 3.3 V input open and no load on the high-voltage output, the high-side pull-up drives that output to 24 V. A continuity beep or an open-circuit voltage measurement alone cannot distinguish this intended resistive path from a damaged semiconductor.
A hard short behaves differently. It presents low resistance after stored charge has dissipated, produces substantially more current when energized, and usually prevents normal logic control of the node. A damaged MOSFET can also leak, clamp, or conduct permanently after excessive VGS; replace suspect devices before evaluating the corrected circuit.
PCB parasitic capacitance and meter input impedance can make disconnected copper retain or display a voltage temporarily. Timing separates that effect from a pull-up: a capacitive node decays after power removal, while an energized pull-up maintains the voltage. Use resistance checks only on a de-energized, discharged board.
Interface approach comparison
| Approach | Advantage | Deciding constraint | Primary risk |
|---|---|---|---|
| Correct the existing bidirectional MOSFET interface | Retains operation in both signal directions | Each gate must connect to its specified supply rail, and every device must remain within its voltage and current ratings | The previous wiring may already have exposed the high-side MOSFET to 24 V VGS, above its 20 V maximum |
| Use a purpose-built unidirectional input or output interface | Separates the requirements of PLC-to-Pi and Pi-to-PLC signals | Select the circuit from the PLC channel type, input current, output-low voltage, Pi thresholds, and required isolation | Using one generic channel for both directions can assign PLC load current to the Pi or present an invalid low level to it |
For a board already built and requiring bidirectional behavior, correct the gate wiring first and replace any overstressed MOSFETs. For signals that travel in only one direction, a purpose-built interface is the better engineering choice because the two directions have different electrical jobs.
When driving a PLC input, this circuit behaves like an NPN sensor: it signals the active state by sinking current. The Pi-side switching path must therefore sink all current demanded by the PLC input. When receiving from a PLC output, the PLC channel must pull the translated node low enough for the Pi to recognize a valid logic zero.
Unpowered diagnostic checks
- Disconnect both 3.3 V and 24 V supplies and discharge the board.
- Compare the PCB schematic and layout with the application circuit pin by pin. Trace each MOSFET gate, source, and drain from the physical package rather than relying only on net labels.
- Confirm that the gates connect to the low-voltage and high-voltage supplies specified by the circuit, not to the input and output signal nets.
- Measure resistance from each apparently unrelated trace to 24 V and ground. A pull-up produces a resistive path; a near-zero stable reading points toward a bridge, wrong footprint, solder defect, or failed device.
- Inspect the MOSFET footprint orientation and pin numbering against the exact component datasheet. Gate, source, and drain assignments vary between packages.
- Remove or isolate a suspect MOSFET if resistance remains abnormal. A normal net after removal identifies the device or its footprint area as the fault location.
- Check whether the two voltage domains share a conductive reference or semiconductor signal path. Call the board galvanically isolated only when the implemented barrier provides no conductive path between the domains and the layout maintains the barrier.
Gate correction and controlled power-up
- Reroute each gate to the supply rail specified by the application circuit. Keep the 3.3 V and 24 V pull-ups on their intended sides.
- Replace any MOSFET that may have experienced 24 V
VGS. Operation after overvoltage is not evidence that the gate oxide remains serviceable. - Power the 3.3 V side first with the PLC disconnected. Confirm that no Pi-facing node rises above its intended 3.3 V domain.
- Apply the 24 V supply with current limiting appropriate to the assembled board. Watch supply current and component temperature while leaving the signal unloaded.
- Measure
VGSdirectly at each MOSFET. Repeat during power-up, power-down, and commanded switching because rail sequencing can create stress that is absent at steady state. - Test logic states using a controlled load before attaching the Pi or PLC. Verify open/high operation and commanded low operation on both sides.
- Connect the PLC input only after reading its input-current specification. Confirm that the sinking path can carry that current without exceeding the Pi-side output or interface-device rating.
- Connect a PLC output only after measuring its loaded low voltage. Compare that value at the Pi pin with the Pi input-low threshold.
Loaded verification and recurring pitfalls
Verify the interface as an electrical load, not merely as a logic diagram. Record high voltage, low voltage, sink current, and device temperature for every channel. Exercise simultaneous channels if the board is multipole because total current and shared copper can raise thermal load even when each individual signal works.
Repeat measurements for every relevant power sequence: 3.3 V only, 24 V only, both supplies, power-up, and power-down. Watch for back-powering, where an energized signal path feeds an unpowered domain. The acceptance criterion is that Pi-facing nodes remain within their device ratings and no MOSFET exceeds its voltage, current, or thermal limits.
Common mistakes include treating an open input as logic zero, measuring voltage without a load, confusing level translation with galvanic isolation, and assuming every PLC channel has the same input or output circuit. Read the electrical table for the exact PLC channel and Raspberry Pi interface before committing the final PCB revision.
FAQ
Why does an unconnected PLC interface trace measure 24 V?
The high-side pull-up drives an open node to 24 V, and the meter draws too little current to pull it down. Test the node under its intended load before treating the reading as a short.
Why does moving the MOSFET gate connection matter?
Tying the gate to an input or output can expose the high-side device to 24 V VGS, exceeding its stated 20 V maximum. Connect each gate to the supply rail specified by the application circuit.
Why does the Raspberry Pi have to sink the PLC input current?
Used as an NPN-style interface, the circuit activates the PLC input by pulling it low. The Pi-side switching path therefore carries the PLC channel's full input current, which must be checked against the interface and Pi ratings.
When should I stop troubleshooting and contact official support?
Stop if the corrected circuit still places more than the 20 V maximum across the MOSFET gate and source, if a Pi-facing node can reach the 24 V domain, or if the required PLC current and logic thresholds cannot be obtained from the product documentation. Keep the Pi and PLC disconnected, record the schematic, measured rail voltages, VGS, loaded current, and power sequence, then escalate to the relevant manufacturer's official support channel.