Programming Omron CP1L Analog Input with RS232 Setpoint

Application Overview

The control task is a classic position/level follower. The PLC receives a numeric setpoint over RS232 (typically a hex or BCD code from a host controller, HMI, or instrument), reads an analog feedback value from a potentiometer or transducer, and energises an output (or a pair of raise/lower outputs) until the feedback equals the setpoint. The architecture fits any Omron CP1L, CP1E, CP1H, CJ2M, or CS1 platform. This guide uses the CP1L-M30/M40DR-A as the reference CPU because it integrates two 12-bit analog inputs directly on the unit, removing the need for an expansion module for small machines.

The four logical steps from the source specification map cleanly onto the standard Omron instruction set:

1. Receive a hex value from a remote device into DM area — use the RXD instruction on serial port 1 (built-in RS-232C) or port 2 (option board CP1W-CIF01).
2. Read a hex value from an analog input — the CP1L-M resolves the voltage across the analog terminal to a 12-bit word in CIO 200/CIO 201 (raw 0x0000–0x0FFF).
3. Compute the deviation — use signed subtraction (- or CLS) and a deadband comparator.
4. Drive the output — use OUT, SET/RSET, or a full PID block to command a relay, transistor, or analog output until the deviation is inside the deadband.

Prerequisites

• CP1L-M30DR-A (or CP1L-M40DR-A) with built-in analog. For external I/O, an CP1W-AD041 (4 AI, 1/6000 resolution) or CP1W-AD042 (4 AI, 1/12000 resolution) module on a CP1L-L or CP1E base.
• CX-Programmer 9.x or Sysmac Studio 1.4x with CP1L support (firmware 1.0 or later is sufficient for these instructions).
• RS-232C option board CP1W-CIF01 if the host uses a DB-9 (PC-style) cable and the CPU only has RS-485. The built-in port on CP1L-EM/EL is RS-485; CP1L-M/CP1H-Y have a built-in RS-232C.
• 10 kΩ linear potentiometer (or 4–20 mA transducer) wired to the analog input terminals as described below.
• A reference document: the CP1L CPU Unit Operation Manual (Cat. No. W462-E1), section 4 (I/O Memory) and section 5 (Built-in Analog).

Hardware Selection and Wiring

The CP1L-M30DR-A exposes a two-channel analog sub-assembly on the top-left of the unit. Pinout from the CPU manual:

Wiring rules that prevent the most common field failures:

1. Use shielded twisted pair for any cable longer than 0.5 m. Ground the shield at the PLC end only.
2. For a potentiometer: connect one end of the track to V+, the wiper to VIN0, and the other end to COM. On the CP1L-M, the +24 VDC terminal cannot source enough current for a 10 kΩ pot; use an external 24 V supply referenced to the CPU's functional earth (FE) terminal.
3. For 4–20 mA transducers: the current input is a sinking loop. Connect the transducer positive to the +24 V external supply, the negative to IIN0, and COM to the same supply's 0 V.
4. Set the channel range DIP switch on the side of the CP1L-M to "V" or "I" as appropriate. The PLC Setup range code must match the switch; mismatches force the channel to 0000 hex with no error bit.

For more details on shielding and signal conditioning, the National Instruments primer on field wiring and noise considerations for analog signals covers the general principles. Microchip's application note "Maximizing the Signal" discusses the input-impedance and settling-time factors that also apply to PLC ADCs.

Analog Input Module Configuration

The CP1L-M's built-in analog resolves to 12 bits (0–4095 decimal) for 0–10 V and 0–20 mA ranges. Enable and configure the channels through PLC Setup → Built-in AD in CX-Programmer (or the equivalent tab in Sysmac Studio). The relevant default parameters:

For external CP1W-AD041 modules, the address allocation is shifted by the unit number (U). A CP1W-AD041 mounted as unit 1 occupies CIO 200–CIO 203 (4 channels, 0000–1770 hex for 0–10 V at 1/6000 resolution) and writes the engineering-scaled value to D200–D203 after SCL2 processing is performed in the ladder.

RS232 Communication Setup

The CP1L serial port (built-in RS-232C on the M/EM types, or the CP1W-CIF01 option board on the L/EL types) is configured in PLC Setup → Serial Port 1 (or 2). The two key parameters for the setpoint stream:

When the host sends a fixed frame such as <STX> 0x12 0x34 <CR> (setpoint 0x1234), the PLC's RXD instruction will deposit the two payload bytes into consecutive DM words beginning at the destination. The format is:

RXD(235) D C N

• D — first destination word (e.g., D100). The raw bytes land low-byte-first because Omron stores words little-endian in the DM area.
• C — control word: 0000 for port 1, 0001 for port 2, 0100 for port 1 with no start/end code match (i.e., accept any byte).
• N — number of bytes to receive (0–256). Setting N=2 for the example above reads exactly the setpoint payload.

The RXD instruction is edge-triggered; in practice the application ties it to a periodic pulse from a 50 ms or 100 ms timer (TIM 0 #50) or to a host-issued "ready" handshake bit mapped to a CIO input.

Memory Map and Variable Allocation

Use a clean allocation so that the receive buffer, scaling, and PID block do not collide. A typical layout for the CP1L-M reference design:

The Working (W) area is preferred for derived boolean flags because it is non-retentive; on power-up all W bits clear automatically, which is the correct default for a follower that must re-acquire the setpoint before driving outputs.

Analog Signal Conditioning and Scaling

The raw ADC count from CIO 200 is not the engineering value the user needs to compare against the setpoint. Two stages of conditioning are typical:

Stage 1: Linear scaling with SCL2

SCL2(486) S D1 D2 R converts a binary source word to a BCD result over an arbitrary span:

• S = D1 (PV_RAW)
• D1, D2 = control block of three words: D100 (input min = 0), D101 (input max = 4095), D102 (output min = 0)
• The fourth word of the control block is implicit; CX-Programmer allocates D100–D103 for one SCL2 invocation.
• R = D2 (PV_EU). With output range 0–1000 the result represents 0.0–100.0 % of pot travel.

The instruction works on unsigned binary. If the application uses 4–20 mA and treats 4 mA as live zero, perform the offset in a separate MOV to subtract 819 (which is 4 mA at 4095/20 mA) and clamp negative results to zero with a LIMIT block.

Stage 2: Moving-average filtering

The CP1L-M averaging filter set in DM 6617 already provides a 1-to-128 sample moving average. For most mechanical potentiometers, 8 samples is enough to clean 50/60 Hz pickup while keeping loop latency under 50 ms. If a faster response is required, set the filter to 1 and add a software filter in ladder:

PV_RAW_FILT = (7 × PV_RAW_FILT_PREV + PV_RAW) / 8

Implement with MOV and *// using the BSET scratch area in W. Avoid integer divide-by-zero by always dividing the running total first, then adding the new sample.

Comparison and Output Control Logic

Three control strategies are common. Choose based on the actuator (relay, proportional valve, or VFD).

Strategy A — On/Off with deadband (simplest, matches the source spec)

Use two unsigned compares plus the absolute-value trick. The ladder:

 |--[ LD  W0.02 ]--[ OUT W0.00 ]   ; if AT_SETPOINT, latch UP OFF
 |--[ CMP  D3  D4 ]                 ; D3 − D4
 |--[ >  ]--[ OUT W0.00 ]           ; DEV > +deadband → OUT_UP ON
 |--[ < -]--[ OUT W0.01 ]           ; DEV < −deadband → OUT_DN ON
 |--[ ABS D3 ]--[ CMP D10 D4 ]      ; |DEV| ≤ DEADBAND → W0.02 ON

The ABS instruction on CP1L is not present in every firmware revision; an equivalent is to test both DEV > 0 and -DEV > 0 in two parallel rungs. CPS (signed compare) reads cleanly:

 |--[ CPS D3 D4 ]--[ P_GT ]--[ OUT W0.00 ]
 |--[ CPS D3 D4 ]--[ P_LT ]--[ OUT W0.01 ]
 |--[ CPS D3 D4 ]--[ P_EQ ]--[ OR  W0.02 ]--[ OUT W0.02 ]

Strategy B — Incremental (stepper / pulse train)

Replace the boolean outputs with a pulse-rate proportional to |DEV|. Multiply by a gain and drive SPED or PULS on a high-speed output. This is the standard approach for a stepper-driven potentiometer on a CP1H-Y, which exposes 100 kHz pulse outputs on CIO 100.00/CIO 100.01.

Strategy C — PID control (analog actuator)

For proportional valves, the CP1L's PID(190) block gives full PID with auto-tuning. Configure D10–D41 as the working area:

 |--[ P_First_Cycle ]--[ PID D0 D10 D50 ]   ; SP, work, output (0–1000 EU)

The PID output is a 0–1000 integer that maps directly to the analog output DA0 at CIO 210 by MOV. Set the proportional band to roughly 20 % of the pot travel, the integral time to 5 s, and the derivative time to 0 s for a slow hydraulic or pneumatic follower; tighten the proportional band and shorten Ti for fast electromechanical actuators.

Complete Ladder Implementation

The full sequence below ties all stages together. Rung numbers are for reference; the actual implementation in CX-Programmer is a single POUs.

Rung 1: Receive the setpoint each cycle (50 ms tick)
 |--[ TIM 0 #50 ]--[ RXD D100 #0000 #0002 ]
After successful RXD, swap the two bytes if the host sends big-endian:
 |--[ MOVB D101.0 D0.8 #8 ]--[ SWAP D0 ]
Or, in most protocols the host already sends little-endian and the swap is unnecessary.

Rung 2: Read built-in analog channel 0
 |--[ MOV CIO200 D1 ]                 ; raw ADC count

Rung 3: Scale raw to 0–1000 EU
 |--[ SCL2 D1 D100 D2 ]               ; D100–D103 are the SCL2 control block

Rung 4: Signed deviation
 |--[ -  D0 D2 D3 ]                   ; D3 = SP − PV (signed)

Rung 5: Drive outputs
 |--[ CPS D3 D4 ]--[ P_GT ]--[ OUT W0.00 ]
 |--[ CPS D3 D4 ]--[ P_LT ]--[ OUT W0.01 ]
 |--[ CPS D3 D4 ]--[ P_EQ ]--[ OR W0.02 ]--[ OUT W0.02 ]

Rung 6: Re-trigger on first scan and clear latches on E-STOP
 |--[ P_First_Cycle ]--[ RSET W0.00 ]--[ RSET W0.01 ]
 |--[ CIO 0.00 ]--[ RSET W0.00 ]--[ RSET W0.01 ]

The hardware outputs 100.00 (UP) and 100.01 (DN) on the CP1L-M30DR-A are wired to the actuator contactor. Internal relays W0.00/W0.01 drive the physical outputs through OUT 100.00 and OUT 100.01 on dedicated rungs to keep the logic and wiring decoupled.

Verification and Commissioning

1. Power the CPU with no field wiring. In CX-Programmer, open the I/O Monitor and confirm CIO 200 reads a stable 0x0000–0x0FFF when you ground VIN0 (should be near 0x0000) and when you apply 10.0 V (should be ≥ 0x0F00). If the read stays at 0000, check the DIP switch range and DM 6602 setting.
2. Connect a terminal emulator (Tera Term, PuTTY) to the CP1L serial port at 9 600-8-N-1. Send STX 0x12 0x34 CR. Watch D0 in the watch window — it should show 0x1234 after the next RXD scan.
3. Force D0 to 500 (50.0 %) and rotate the pot. The UP output should energise below 50 % and the DN output above 50 %; both should release between, say, 49.5 % and 50.5 % if DEADBAND is 5.
4. Disconnect the host and verify that the PLC does not latch the last good setpoint into a new motion. CP1L DM area is retained through power cycle, so add a watchdog that clears D0 if no valid RXD has been received within 5 s.
5. Document the scaling constants in the PLC Setup comments so the next engineer can reverse-engineer the scaling without running the math.

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