Quadriga S5 PLC Programming: Implementing Counters Using COMP

Quadriga is a DOS-based programming environment sold in the United Kingdom by Pantek for use with Siemens S5 series programmable logic controllers. The package is menu-driven and function-key driven, giving engineers a structured workflow for creating, editing, and documenting S5 programs. Unlike modern Siemens tooling such as TIA Portal or the historical STEP 7, Quadriga was designed for an era of monochrome monitors, keyboard shortcuts, and direct keyboard entry rather than graphical drag-and-drop. Engineers moving onto S5 machinery from platforms such as Mitsubishi GX Works, GX Developer, or Medoc typically find Quadriga austere but predictable once the menu structure is mapped out.

This reference covers the practical knowledge needed to make minor modifications to existing S5 programs in Quadriga, with a specific focus on counter implementation. The source-of-truth for this article is the workflow used by engineers who have kept S5 systems in production long after the platform was officially superseded by the S7 family, together with the documented counter and timer behavior of the S5 CPU firmware itself.

Overview of Quadriga and the S5 Environment

Quadriga is one of several third-party S5 programming packages that circulated in the United Kingdom during the 1990s. Pantek, the distributor referenced in field discussions, was also the company marketing Wonderware InTouch in the UK at the time, which is why Quadriga installations are often found on the same engineering benches as early Wonderware HMI nodes. The two product lines were sold through the same channel but were never technically integrated at the PLC programming level.

Quadriga's primary value proposition is offline S5 program development and documentation. It can edit the same program files that Siemens' own STEP 5 tools produce, and it can communicate with the PLC through the standard Siemens programming cable (typically the AS511 protocol over a serial COM port). Engineers using Quadriga can:

• Open and edit existing S5 program files (DOT, S5D, or SEQ blocks depending on version)
• Insert, delete, and modify ladder network elements using either the menu bar or function keys
• Document I/O assignments, symbol names, and operator comments in a project file
• Transfer compiled programs to and from the CPU over the programming port
• Use a watch/status view to monitor flag, input, output, timer, and counter values online

Siemens S5 PLC Family Context

Before working with Quadriga, it helps to understand the CPU families it targets. The Siemens SIMATIC S5 range spanned roughly 1979 through the late 1990s and was organized by increasing capability:

All S5 counters store a 16-bit BCD value in the range 0–999 in their assigned counter word. All S5 timers store a 16-bit BCD time value in the same 0–999 numeric range, interpreted as either hundredths of a second (0.01 s base) or tenths of a second (0.1 s base) depending on the timer function block selected. The exact set of available counter and timer words depends on the CPU type and the configured area allocation in the system data word.

Three programming representations are supported in S5: Ladder Diagram (LAD/KOP), Control System Flowchart (CSF/FUP), and Statement List (STL/AWL). Quadriga supports all three, with the editor switching between representations only where the underlying logic allows it.

Quadriga Interface and Navigation Model

Quadriga is invoked from a DOS command line, typically with the program name and a project file argument. Once running, the user interacts through a top menu bar and a row of function-key shortcuts at the bottom of the screen. The most common key conventions are:

• F1 / Shift-F1 – context-sensitive help, also lists the available operations in the current program block type
• F2 – open file / load program from disk
• F3 – save the current program to disk
• F4 – begin a new ladder segment / network
• F5 – insert an element at the cursor (contact, coil, function block)
• F6 – delete the element at the cursor
• F7 – transfer program to PLC (PC → AG)
• F8 – transfer program from PLC (AG → PC)
• F9 – start online status / watch view

Function-key assignments can vary between Quadriga versions, so always confirm by pressing F1 at the top-level menu. If F1 lists the available functions, the version is consistent with the convention above. If the assignment is different, follow the on-screen F-key labels rather than assuming the defaults from memory.

Counter Programming: The COMP Pattern

The single most important behavior difference between timers and counters in S5 that catches new users coming from Mitsubishi is this: timer function blocks accept a preset (TW) value, but counter function blocks do not. A counter word (C) only ever holds the current count. It has no internal setpoint register.

To implement a counter with a preset in S5 you therefore combine two operations:

1. A counter function block (CU, CD, or C) that increments or decrements the counter word on each input pulse
2. A COMP (comparison) function block that watches the counter word and produces a boolean result when the count crosses the threshold you want

The COMP function is the standard S5 comparator. It evaluates two operands and outputs a logical 1 (signal state 1) when the comparison is true. The output of COMP is wired into a coil, a flag, or another operation just like any contact result.

Why the COMP pattern exists

This is not a Quadriga limitation. It is the underlying STEP 5 language. The S5 instruction set deliberately separates counting from comparison so that a single counter can drive multiple threshold outputs — e.g., one coil at 10 counts, another at 50 counts, a third at 100 counts — by simply duplicating the COMP block with different thresholds. If the counter had an internal preset, you would be limited to a single threshold per counter word.

Comparison Operators in Quadriga

The COMP function supports the standard set of S5 relational operators. In Quadriga, these are selected from a menu prompt or typed directly into the COMP block’s operand entry:

Note the use of >< (two separate characters) as the display form of the not-equal operator in the S5 text representation. This convention is preserved in Quadriga menus and in any printed program documentation.

Step-by-Step: Adding a Counter with COMP in Quadriga

The following procedure assumes you are editing an existing program in Quadriga and want to add a counted-event output that activates once a counter has accumulated 10 pulses on an input.

Prerequisites

• Quadriga installed and configured for the COM port your S5 CPU is wired to (COM1 or COM2, 9600 baud, AS511 protocol)
• Working copy of the project file (.S5D or directory structure, depending on version)
• Verified current backup of the CPU program (F8 / read from PLC, save as a dated filename)
• Symbol table open with the inputs, outputs, counters, and flags you plan to use already named

Procedure

1. Open the project. Press F2, navigate to the project directory, and load the program file. If you are working with a multi-block S5 program, identify the OB, PB, or FB block where the new counter logic will live — typically the same block that contains related I/O, or a free PB if you want to keep the change isolated.
2. Navigate to an empty network. Use the page keys or the menu-driven Go To dialog to reach a network with free space at the right-hand rail. Press F4 to start a new network if needed.
3. Place the count input contact. Press F5 to insert, select a normally-open contact (NO / —|—), and assign it to the input bit that produces the pulse you want to count. For example, assign the contact to I 0.1 (input byte 0, bit 1) or to its symbolic name if one exists.
4. Insert the counter function block. Press F5 again and select the counter function. In Quadriga the function is labeled simply as CU (count up), CD (count down), or C (count, with separate up/down inputs). Select CU for the common case. Assign the counter word to an unused counter, e.g., C 10.
5. Place the COMP block. Press F5 and select the COMP function from the comparator list. Quadriga will prompt for the comparison operator; select >= if you want the output to assert at the threshold and stay asserted, or == if you want a single-count pulse at exactly the target value.
6. Enter the COMP operands. The COMP block has two operand fields. Fill them as:
   • Operand 1: the counter word you used, e.g., C 10
   • Operand 2: the threshold constant, e.g., KF +10 (KF denotes a fixed-point constant in STEP 5)
7. Wire the COMP output. Place a coil (—( )—) at the right-hand power rail and assign it to the output you want to drive, e.g., Q 1.0 or its symbol. Optionally also drive a flag (e.g., F 20.0) so other networks can react to the threshold.
8. Add a reset for the counter. Counters latch in S5; they hold their count value even after the count input stops. Add a separate network with a normally-open contact tied to your reset condition (a manual pushbutton input, a startup flag, or an end-of-cycle flag) wired into the CR (counter reset) function on C 10. Without a reset path the counter will accumulate forever and your threshold logic will only ever fire once.
9. Document the network. Use the network comment field (typically Shift-F4 or the menu → Edit → Comment) to record what this network does, the counter number, the threshold, and the date of the change. The S5 is famously under-documented, and the engineer who maintains the machine next will thank you.
10. Save the file. Press F3 to save. Then compile the block (the menu path is typically Program → Compile, or the shortcut Ctrl-F9 in some Quadriga versions) to produce the machine code that the CPU understands.
11. Transfer to the CPU. Connect the programming cable, ensure the CPU is in STOP with the key switch, and press F7 (or the equivalent PC → AG menu item) to download the modified block. Watch the transfer log for errors.
12. Switch to RUN and test. Turn the key switch to RUN. Use F9 / status view to watch the counter word increment on each input pulse, and verify the output energizes at the threshold value.

Working with Timers vs Counters

If you arrived at counter logic by first building a timer-based solution (a common workaround when the counter/preset pattern is not yet understood), the following table summarises the behavioral differences you will need to address when migrating to the proper counter+COMP pattern.

Rule of thumb: if the parameter you are comparing is a number of events (parts, cycles, pulses, button presses), use a counter. If the parameter is a duration, use a timer. Do not try to fake a count with a slow timer pulse — the substitution is fragile, drifts with CPU scan time, and is hard to read in code review.

Verification and Commissioning

Once the modified block has been transferred to the CPU, verify the logic in a controlled sequence before restoring production. The recommended order is:

1. Force the count input manually. Use the machine’s manual/jog controls to produce one pulse at a time, or use Quadriga’s status view to force the input bit high and low. Watch the counter word increment by exactly one per pulse. If it increments by more than one per pulse, the input is not debounced — add a timer-based debounce network feeding the CU input.
2. Confirm the threshold trip. Pulse the input until the counter crosses the threshold you configured in COMP. Verify that the target output or flag transitions to 1 at exactly the right count. For a >= comparison, the output should assert at the threshold count and stay asserted on subsequent counts.
3. Test the reset path. Activate your reset condition. Confirm that the counter word returns to 0 and that any output driven by the COMP result drops off appropriately. If the output remains stuck on after reset, the COMP block is being driven by a flag that was latched separately — add a reset network for that flag as well.
4. Test the boundary cases.
   • Threshold = 1: confirm the output asserts on the first pulse and resets on reset.
   • Threshold = 999 (max BCD): confirm the counter does not roll over silently — S5 counters saturate at 999, they do not wrap to 0, but the COMP result will be permanently true above 999 and any reset network becomes critical.
   • Threshold = 0: this is technically valid but trivially true at all times after the first pulse. Use it deliberately (e.g., to flag “any count has occurred”) or rewrite as a direct input edge detector.
5. Cycle the CPU. Stop and restart the CPU. If the counter is configured as retentive, the value should survive; if not, it should reset to 0. Verify the behavior matches the machine’s operational expectations. If retention is desired and missing, change the system data word to flag the counter word as retentive, then re-transfer the system data block.
6. Run a full operational cycle. Put the machine through one complete production cycle under normal operator control. Confirm that the counter logic interacts correctly with the surrounding program — in particular, that no other network is also writing to the same counter word, and that no other network is also writing to the output you are now driving.

Common Issues and Field Notes

The following matrix captures the most frequent failure modes encountered when adding a counter to an S5 program in Quadriga, with the underlying cause and the recommended corrective action.

Migrating Away from Quadriga

Quadriga is a maintenance tool, not a development platform for new machinery. If the S5 systems you are maintaining will be in service for more than another 2–3 years, plan a migration to the S7-300 / S7-400 family (using STEP 7 V5.5) or to the S7-1500 (using TIA Portal). The Siemens S5 to S7 migration guide, available through the Siemens Industry Online Support portal, documents the symbol mapping and program conversion utility. When migrating a counter+COMP pattern, the S7 equivalent is a single CTU (count up) IEC timer/counter block with a PV (preset value) input — the behavior you have been emulating in S5 with two separate blocks is native to a single S7 block.

For documentation purposes, when handing over a system that is about to be migrated, ensure the Quadriga project includes:

• A printed symbol table with all inputs, outputs, flags, timers, and counters named
• Network comments on every network added or modified
• A change log recording the date, the engineer, and the purpose of each modification
• A backup of the compiled block on the engineering PC and on a separate media (USB, CD, network share)

This is the difference between an S5 program that can be converted in an afternoon and one that requires a full week of reverse engineering to understand.