Reading Siemens STL Logic: A, O, R, S Bit Instructions Explained

Overview

Statement List (STL) is the textual instruction set for the Siemens SIMATIC S7-300 and S7-400 controller families. Although most STEP 7 projects today use Ladder Diagram (LAD) or Function Block Diagram (FBD) editors, a large installed base of S7-300/400 firmware still ships with STL networks that must be read, audited, and modified in the field. STL is also the lowest-level view in STEP 7 (and remains present in TIA Portal as an option for S7-300/400-compatible blocks), so engineers migrating legacy code, troubleshooting interlocking logic, or adding conditions to alarm networks must understand how the STL scan evaluates statements from top to bottom within a network.

The reference for the entire bit-logic instruction set in this article is the Siemens manual STEP 7 - Statement List (STL) for S7-300 and S7-400 Programming. The examples below use the exact mnemonics, operand formats (DB, DBX, byte.bit), and evaluation rules documented in that manual so the code can be copied into STEP 7 V5.x or TIA Portal with no translation.

STL Bit Logic Instruction Set

The STL bit-logic instruction set operates on the accumulator-1 bit (RLO — Result of Logic Operation) and the Status Word. The most relevant instructions for reading alarm logic are listed below. Full coverage is in the Siemens STL manual chapter 1, "Bit Logic Instructions."

The RLO is the Boolean accumulator that STL uses to carry the partial result from one statement to the next. Every A or O reads its operand and combines that operand with the current RLO; every S, R, or = consumes the RLO when it executes.

Reading STL Networks: The Top-to-Bottom Rule

Within a single STL network, statements execute strictly top-to-bottom. Each A or O modifies the RLO based on the bit just scanned; each S or R writes to its destination bit conditional on the current RLO. There is no implicit parenthesis group — the result of a network is whatever the RLO holds after the last statement that consumed it.

Consider a typical alarm network written in STL:

NETWORK 1   // Alarm 100 disable
      A     DB1205.DBX15.7        // RLO = DB1205.DBX15.7
      R     DB1205.DBX100.0       // if RLO=1, reset alarm 100
      A     DB1205.DBX15.6        // RLO = DB1205.DBX15.6
      S     DB1205.DBX100.0       // if RLO=1, set alarm 100
      NOP   0

To read this network, evaluate each statement in order:

1. Statement 1 — Scan DB1205.DBX15.7 and AND it into the RLO. RLO becomes the value of that bit.
2. Statement 2 — If the current RLO is 1, reset DB1205.DBX100.0. The RLO is consumed but not modified.
3. Statement 3 — Scan DB1205.DBX15.6 and AND it into the RLO. Because statement 2 was a reset (not an A), the RLO does not retain the value used for the reset — it is replaced by the new scan of DB1205.DBX15.6.
4. Statement 4 — If the current RLO is 1, set DB1205.DBX100.0.

The net effect: when both DBX15.7 (disable condition) and DBX15.6 (set condition) are true, the reset runs first and then the set runs, leaving DBX100.0 set. This is why reading STL purely from the screen capture alone can be misleading — the order of statements, not their count, determines the result.

Set/Reset Behavior in STL

The S and R instructions are conditional on the RLO at the moment they execute. They do not maintain a latch flag — the bit itself is latched, but the controlling RLO is recomputed from the network each scan cycle. Therefore, two S/R statements in the same network can both touch the same destination bit on the same scan, and the statement that appears last wins.

This table is the single most important reference when reading STL alarm logic: scan order, not the Boolean operator, governs which statement writes last.

Adding an OR Condition to an STL Network

The original engineering question asked how to add a second disable bit — DB1205.DBX87.7 — so the alarm is disabled when either DBX15.7 or DBX87.7 is true. The STL instruction is O (OR). Place it directly under the existing A statement that establishes the disable condition; the O enters its operand into the RLO as a parallel branch.

NETWORK 1   // Alarm 100 disable (extended)
      A     DB1205.DBX15.7        // RLO = DBX15.7
      O     DB1205.DBX87.7        // RLO = RLO OR DBX87.7  (disable if either)
      R     DB1205.DBX100.0       // if RLO=1, reset alarm 100
      A     DB1205.DBX15.6        // RLO = DBX15.6  (previous RLO is replaced)
      S     DB1205.DBX100.0       // if RLO=1, set alarm 100
      NOP   0

The logic now reads as the following plain-English sequence:

• If DBX15.7 OR DBX87.7 is true, reset alarm DBX100.0.
• Then evaluate DBX15.6 on its own and, if true, set alarm DBX100.0.

The disable condition (OR pair) and the enable condition (DBX15.6) are not combined with one another because R and S consume the RLO without producing a new one — the second A starts a fresh scan.

Multiple OR Conditions and Parenthesis Equivalents

When more than two OR conditions feed the same reset, chain additional O statements. For nested expressions such as (A AND B) OR (C AND D), use A, O, parentheses with ( and ), and the nesting operators A(, O(, ) as defined in the STL manual.

NETWORK 2   // Complex alarm latch logic
      A     I 0.0                  // start scan
      A     M 10.0                 // nested AND
      O                              // begin OR branch
      A     I 0.1
      A     M 10.1
      )                              // close OR branch
      S     DB1205.DBX100.0         // set alarm if combined RLO = 1
      A     DB1205.DBX15.7
      O     DB1205.DBX87.7
      R     DB1205.DBX100.0

The parentheses nest one level; deeper nesting is allowed by adding more ( / ) pairs. Every open parenthesis must have a matching close parenthesis before the consuming statement executes, otherwise STL throws a syntax error at compile.

Operand Address Format

STL addresses bits inside a data block as DB<n>.DBX<byte>.<bit>. In the example, DB1205.DBX15.7 means data block 1205, byte 15, bit 7. Byte and bit numbering are decimal. Some STEP 7 displays and printers show these as DB1205.DBX 15.7 with a space; the space is cosmetic only and has no semantic effect. After an OPN DB or after the STL block header implicitly opens DB1205, the DB number can be dropped: DBX15.7 is equivalent.

Confirm the DB is opened before scanning DBX bits. If the active DB is a different number, every DBX read goes to that other block, which is a common source of phantom failures during maintenance.

Troubleshooting Matrix

Verification Procedure After Modification

1. Compile and download the modified FB/FC into the CPU (or do a delta download via TIA Portal if using a V15+ project referencing a legacy S7-300/400 block).
2. Open the block online in STEP 7 and place the cursor on the modified network; use Monitor/Modify with the statement cursor enabled so the CPU highlights the currently executing line.
3. Force DB1205.DBX15.7 = 1 in a Variable Table (VAT). Confirm DB1205.DBX100.0 clears within one OB1 cycle.
4. Force DB1205.DBX87.7 = 1 instead. Confirm DB1205.DBX100.0 clears again. This validates the new OR condition.
5. Force both bits low and force DB1205.DBX15.6 = 1. Confirm the alarm sets.
6. With both disable bits low, force DB1205.DBX15.7 = 1 to clear the alarm while DBX15.6 stays high. Confirm the alarm stays clear after one full scan — this is the test that catches the order-of-statement bug described in the original question.
7. Remove all forces and document the change in the project revision log.

Equivalent Representations in LAD and FBD

For engineers who prefer graphical editors, the same logic translates as follows. STL is a useful pivot because it shows the scan order more explicitly than the graphical views.

LAD equivalent:
  |   DB1205.DBX15.7     DB1205.DBX87.7         |
  |-----| |-----+------| |------------+         |
  |              |                  |         |
  |              +-----[ R DB1205.DBX100.0 ]----|
  |                                        |
  |   DB1205.DBX15.6                       |
  |-----| |---------------[ S DB1205.DBX100.0 ]-|

FBD equivalent:
  DB1205.DBX15.7 ---+
                     |-- ( R ) -- DB1205.DBX100.0
  DB1205.DBX87.7 ---+

  DB1205.DBX15.6 ----- ( S ) -- DB1205.DBX100.0

The Ladder diagram of two parallel contacts feeding a single reset coil is the LAD view of A / O / R; the set coil below it corresponds to the second A / S pair. LAD and FBD editors in STEP 7 generate equivalent STL when compiled.

Best Practices When Modifying Legacy STL

• Document the network order. In S7-300/400 STL, the order of R and S statements on the same destination bit is semantically significant. Add a comment line above each R/S statement explaining why it appears where it does.
• Use a single Set and a single Reset per alarm. Multiple Set statements scattered across networks create exactly the order-of-execution bug discussed above. Centralize alarm control in one network per alarm tag.
• Prefer explicit parenthesis for clarity. Even when A / O sequences are technically unambiguous, adding A( ... ) and O( ... ) nests prevents future maintainers from misreading the network.
• Validate mnemonics. Always check Tools → Options → Mnemonics in STEP 7 before editing. Mixing A and U in the same project causes silent compile errors.
• Cross-reference every alarm bit. Use Options → Cross-References in STEP 7 to find every read and write of DB1205.DBX100.0. Hidden Set statements in other blocks are the most common cause of "alarm will not stay cleared" complaints.
• Keep STL documentation next to the block. The block header and footer in STEP 7 (Block → Block Properties → Comment) supports up to several KB of free-text. Use it for the Boolean description that the screen capture alone cannot convey.

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