Replacing S5-115U CPU 943-7UB11 with -7UB21: Field Procedure

Overview

This procedure covers the urgent field replacement of a Siemens SIMATIC S5-115U central processing unit 6ES5943-7UB11 (CPU 943, single interface) with a spare 6ES5943-7UB21 (CPU 943, dual interface). The two part numbers share the same functional core (CPU 943 instruction set, memory model, and rack footprint) and differ primarily in the number of serial interfaces exposed on the front panel. The replacement is a cold-swap procedure: power down, transfer the EPROM submodule, install the new CPU, perform an overall reset, and re-establish the PG connection.

The steps in this guide assume the spare 6ES5943-7UB21 has been verified as a known-good unit (no battery corrosion, no bent connector pins, valid front-panel labels). For diagnostics prior to the swap that justify the CPU as the failed module, refer to the S5-115U Diagnostics and Troubleshooting Manual on Siemens Industry Online Support.

S5-115U and CPU 943 Family Background

The SIMATIC S5-115U is a modular PLC introduced by Siemens in the 1980s and still in service in plants with long asset life cycles. It uses a central rack (CR) and expansion racks (ER) connected over the IM 305/IM 306 interface modules. The CPU 943 is the high-end CPU of the 115U family and executes STEP 5 programs in three address areas: inputs (I), outputs (Q), and the extended memory used for flags (F), timers (T), counters (C), and data blocks (DB/DX).

Memory architecture of the CPU 943:

• Volatile user memory (RAM) for program and data, backed up by a lithium battery on the CPU front panel
• One socket for a non-volatile memory submodule (EPROM or EEPROM) used for cold-restart loading of the program and default DB contents
• Internal flag/timer/counter areas: 2048 flags (M 0.0–M 255.7), 256 timers (T 0–T 255), 256 counters (C 0–C 255)
• Digital I/O address space: typically 1024 inputs and 1024 outputs addressable (rack-dependent)

The CPU 943 supports the full STEP 5 instruction set including bit (A, AN, O, ON, S, R, =, FP, FN), timer/counter (SP, SE, SD, SS, SF, R, CU, CD), load/transfer (L, T), comparison (=, <>, >, >=, <, <=), arithmetic (+, –, x, :), block calls (JU/JC to PB, FB, OB, SB, FX), and the integrated floating-point operations available on CPU 943 and higher.

For architecture details, see the S5-115U Programmable Controller Manual and the S5-115U CPU 94x Operating Instructions.

Part Number Comparison: 6ES5943-7UB11 vs 6ES5943-7UB21

The functional core of both part numbers is identical. The -7UB21 adds a second physical interface (IF2) on the front panel; the address assignment, flag/timer/counter map, and STEP 5 instruction behavior are unchanged. In practice, a program written and tested on a -7UB11 runs unmodified on a -7UB21, and vice versa.

Hardware Compatibility Analysis

Before performing the swap, confirm the following compatibility points:

1. Rack slot. Both CPUs use the same physical form factor and connector. Insert the replacement into the same slot from which the original was removed. Do not attempt to seat a CPU in a slot designated for an I/O module.
2. Power supply budget. The CPU 943 draws from the 5 V DC rail of the rack backplane. Ensure the installed power supply (for example 6ES5951-7LD21 or 6ES5951-7NB21, depending on voltage class) has margin for the CPU replacement. Like-for-like CPU swaps are typically neutral on the 5 V budget.
3. Battery. Verify that the lithium backup battery in the -7UB21 is healthy (voltage > 3.4 V, no swelling, no leakage). A depleted battery in the spare will cause a cold restart / memory loss the first time the system is powered down for any reason. A new battery should be installed before commissioning if the age is unknown.
4. Interface usage. Identify which interface the active PG/OP or SINEC L1 connection uses. On the -7UB11 the only choice is IF1. On the -7UB21 the same PG cable must be reconnected to the IF1 socket. The IF2 socket on the -7UB21 may be used for a second PG/OP or for SINEC L1; do not cross them unless the program was written to expect that mapping.
5. Memory submodule. The EPROM/EEPROM submodule from the failed CPU is the program carrier. It must be physically transferred to the replacement.

For CPU 943 electrical and mechanical specifications, see the S5-115U CPU 94x Operating Instructions.

Prerequisites for Replacement

• Spare CPU 6ES5943-7UB21 in known-good condition, visually inspected for damage
• ESD wrist strap and grounded mat
• Small flat-blade screwdriver for connector screws and the front-panel cover
• Documentation of the active STEP 5 program and the DB default contents (in case the EPROM is unreadable)
• PG 720 / PG 740 / PG 760 (or equivalent) with STEP 5 programming software and a working serial cable to connect to IF1
• Access to the upstream disconnect so the rack can be de-energized safely
• Functional knowledge of the plant process and permission to restart the affected section

EPROM Memory Submodule Transfer

The CPU 943 holds the non-volatile copy of the STEP 5 program in a single submodule located behind a small access cover on the upper portion of the front panel. The submodule is keyed and can only be installed in one orientation. Use the following handling rules:

• Power the rack down completely before removing the submodule. Hot removal will not damage a standard EPROM, but it can cause a RAM/DB corruption event in the running CPU that is then promoted to the cold-restart copy at the next save.
• Avoid touching the submodule contacts. Skin oils and static discharge are the two principal failure mechanisms for EPROM submodules in service.
• Label the submodule with the slot origin, program name, version, and date before removal. This is the only reliable way to keep multiple spare EPROMs sorted in a working spares pool.
• If the original EPROM is suspected unreadable (intermittent restart, repeated BAU/PUV faults), do not transfer it. Use a PG to read the still-backed-up RAM contents (CPU 943 must be in STOP with a healthy battery) and re-burn a new EPROM before swapping CPUs.

For submodule catalog numbers compatible with the CPU 943 socket, refer to the S5-115U Manual appendix on memory submodules.

Step-by-Step Replacement Procedure

1. Isolate and de-energize the rack. Open the upstream disconnect and lock-out / tag-out (LOTO) per site procedure. Confirm the 24 V DC and 5 V DC rails are at 0 V with a meter before proceeding.
2. Record the operator panel and PG connections. Photograph the front panel of the failed CPU and the cable connections on IF1 (and IF2 if any). Note the cable labels so they can be reconnected to the same logical port on the replacement.
3. Disconnect IF cables. Unscrew the IF1 (and IF2, if present) cable connectors and lift them out of the sockets. Do not pull on the cable; use the connector shell.
4. Remove the failed CPU. Using a flat-blade screwdriver, loosen the two captive screws at the top and bottom of the CPU front plate. Pull the module straight out of the rack using the front handle. Place it in an ESD bag.
5. Open the memory submodule cover on the failed CPU. The cover is the small rectangular plate above the mode selector. Remove the cover and lift the EPROM submodule straight out of its socket using an extractor tool or carefully with fingers, gripping the plastic body — never the contacts or the glass window.
6. Inspect the spare 6ES5943-7UB21. Confirm the battery voltage, check the front panel for cracks, verify the connector pins are not bent or oxidized, and visually inspect the EPROM socket for foreign material.
7. Install the EPROM into the spare CPU. Orient the submodule so that the keyed notch matches the socket. Press firmly and evenly until the submodule seats flush. Replace the cover.
8. Insert the replacement CPU into the rack. Slide the module into the original slot and tighten the captive screws. The module should seat fully; if there is resistance, stop and re-check alignment rather than forcing it.
9. Reconnect IF cables. Reconnect the IF1 cable to IF1 of the new CPU, matching the photo taken in step 2. If the original -7UB11 had a single interface and the new -7UB21 has two, leave IF2 disconnected unless the program was written to use it.
10. Remove LOTO and re-apply power. Restore the upstream disconnect. The CPU should power up and the front-panel LEDs should indicate a defined state (see the verification section below).

Overall Reset (Memory Clear) Procedure

After a CPU swap, the RAM contents of the new CPU are uninitialized. STEP 5 expects the RAM image to be reloaded from the EPROM during a cold restart. The standard CPU 943 overall reset (memory clear) procedure is:

1. Set the mode selector to STOP.
2. Set the mode selector to RUN while holding the reset position (the third switch position on the CPU 943 selector). The exact mechanic depends on the front-panel revision; on most CPU 943 units this is performed by rotating the selector past STOP into the momentary reset position and back to RUN, which triggers a cold restart with memory initialization.
3. Observe the front-panel LED pattern. A successful overall reset on the CPU 943 returns the CPU to STOP with no active faults (the red fault LED extinguishes after a few seconds).
4. Set the mode selector to RUN again. The CPU performs a cold restart, copies the program and default DBs from the EPROM into RAM, and begins cyclic execution of OB 1.

For the exact switch positions and LED indications of the CPU 943, refer to the CPU 94x Operating Instructions.

Interface Configuration

Both IF1 and IF2 (where present) on the CPU 943 are configured in the DB 1 (or DX 0) data block, using the SS / SL interface parameter syntax. The PG cable uses a 15-pin sub-D to 25-pin sub-D (or TTY current-loop) cable, depending on the PG model. Typical parameters for IF1 as the programming port are:

If the program was running on a -7UB11 with IF1 set as the PG port, the same DB 1 parameter set works on a -7UB21 using IF1. The IF2 interface is enabled only if the DB 1 parameters include an IF2 block; otherwise IF2 is silent. Verify with a PG attach attempt before declaring the interface configuration correct.

Verification and Commissioning

After the CPU is running, perform the following checks before handing the line back to operations:

1. PG attach on IF1. Connect a PG running STEP 5 to IF1 with the known baud rate. Confirm the PG reports the new CPU's order number (6ES5943 7UB21) and the correct program blocks are listed in the catalog.
2. Status check. In STEP 5 online mode, observe the cyclic OB 1 execution, monitor the critical I/O, and confirm the process is in a safe state for startup.
3. Fault buffer. Read the CPU's fault buffer (ISTACK) via the PG. No new faults should be present after the cold restart. Document any pre-existing faults that were carried over from the failed CPU.
4. Battery check. In PG diagnostics (or by measuring the battery test point on the front panel), confirm the backup battery is healthy. Replace any battery that measures below 3.4 V or whose date code is older than the site policy.
5. Process restart. With operations in control, transition the process from a safe state to running. Verify timing of inputs, outputs, interlocks, and operator panel feedback.
6. Documentation update. Update the site asset register, mark the failed CPU 6ES5943-7UB11 as scrap or RMA, and update the spares count for 6ES5943-7UB21.

Troubleshooting Matrix

Spares, Lifecycle, and Migration Notes

The S5-115U is officially discontinued by Siemens. Spare CPUs, EPROM submodules, and front-panel batteries are typically sourced from the secondary spares market. When receiving any S5 spare part, perform a bench test before placing it on the shelf:

• Power the unit on a known-good S5-115U test rack with a healthy power supply
• Perform an overall reset and verify the front-panel LEDs return to the defined "STOP no fault" state
• Run a short test program from a known EPROM and confirm cyclic execution
• Verify the backup battery voltage and date code; replace if outside site policy

For long-term strategy, sites should evaluate migration to a current Siemens controller family (for example S7-1500 with the SIMATIC S5 to S7 Migration Guide) before the S5-115U spares pool is exhausted. The CPU 943 to -7UB21 swap keeps the existing program and I/O in service; a migration to S7-1500 requires re-engineering the program in TIA Portal but preserves the field I/O and most of the STEP 5 program structure via the S5 to S7 converter.

Additional reference: S5-115U Manual, S5-115U CPU 94x Operating Instructions, and the Siemens Industry Online Support entry portal for legacy S5 documentation.

Frequently Asked Questions