Resolving Analog Output Delay in Siemens S7 PLC Systems

Problem Overview

When a sinusoidal analog signal is wired to a Siemens SIMATIC S7-1200 or S7-1500 analog input module (SM), processed by user logic, and then written back out to an analog output module, the reproduced waveform at the output is delayed in time relative to the original input. At low frequencies such as 2.5 Hz, the delay is small in absolute terms (tens of milliseconds), but it becomes visible as a measurable phase shift on an oscilloscope and is unacceptable when the loop is intended to be transparent (e.g., signal retransmission, monitoring taps, or laboratory replication).

The delay is the sum of several cascaded effects:

1. Analog-to-Digital Converter (ADC) conversion time in the input module.
2. Hardware low-pass filter (input smoothing) configured in TIA Portal device configuration.
3. PLC scan time / OB1 cycle time of the user program.
4. Program execution time between the read and write instructions.
5. Digital-to-Analog Converter (DAC) settling time in the output module.
6. Optional firmware-side output smoothing on the analog output channel.

For a 2.5 Hz sine wave, the period T = 1/f = 400 ms. A phase shift of 36° corresponds to 40 ms of delay, which is realistic when the default hardware filter is left active on SM analog channels.

Root Cause Analysis

For the original case (Siemens SIMATIC environment, 2.5 Hz sinus, AI read by PLC then written to AO), the delay is the combined result of four identifiable contributions. Each one must be measured or computed separately to determine where most of the latency is introduced.

1. ADC Conversion Time

Siemens SM 1231 / SM 1331 analog input modules use successive-approximation ADCs. Conversion time per channel is module-dependent:

For a 2.5 Hz signal, ADC conversion delay is negligible (well under 1 ms). It is not the dominant contributor at this frequency.

2. Hardware Input Filter (Dominant Cause)

The default configuration in TIA Portal for SM analog input channels enables a hardware low-pass filter that averages a configurable number of samples. This is the largest single source of latency for most users.

Available filter settings in TIA Portal > Device Configuration > AI channel > "Input / Smoothing":

At 2.5 Hz with a 32-sample average on a 100 ms cyclic update, the equivalent time constant of the filter τ is roughly N·Ts/2 = 32·100 ms / 2 = 1.6 s. The resulting phase shift φ = -arctan(2πf·τ) easily exceeds 80°, producing a visibly lagged sinus at the output.

3. OB1 Cycle Time and User Logic

The default execution model runs the AI read, signal processing, and AO write inside OB1 (the main cyclic program). OB1 cycle time on a stock S7-1214C is typically 1-3 ms for a small program and grows with code size. A 5 ms OB1 cycle adds 5 ms of latency that can vary cycle-to-cycle (jitter).

4. DAC Settling and Output Smoothing

Siemens SM 1232 / SM 532 analog output modules typically have 0.1 ms settling time to 1% for a resistive load. This contribution is sub-millisecond. Some output modules also expose a smoothing configuration; verify it is disabled or set to the minimum.

Solution Path: Configure for Minimum Latency

Step 1 - Reduce the Hardware Input Filter to Minimum

1. Open the project in TIA Portal (V15.1 or later recommended; firmware 4.4 or higher on the CPU).
2. Open Devices & Networks and select the analog input module.
3. For each used channel, open the Properties inspector and locate Inputs > Smoothing (German: Glättung).
4. Set smoothing to None (single-sample, no averaging).
5. For SM 531 high-speed modules, also verify Conversion time is set to the fastest available channel group update rate.
6. Compile and download the hardware configuration to the CPU.

Reference: SIMATIC S7-1200 Programmable Controller System Manual (entry ID 91696622) describes the input filter and its effect on noise versus response time. The S7-1500 equivalent is documented in S7-1500 Automation System System Manual (entry ID 86140384).

Step 2 - Move the AI Read and AO Write into a Fast Cyclic OB

Use a high-priority cyclic interrupt OB (e.g., OB30 to OB38) at a 1-2 ms cycle. Direct I/O access via the I/O address with the :P qualifier bypasses the process image update and reads/writes the peripheral directly, eliminating the OB1 PII/PII delay.

Example Structured Text (SCL) for OB30 (priority 16, 1 ms cycle):

// OB30 - 1 ms cyclic interrupt, priority 16
// Direct peripheral read from AI (IW64:P) and write to AO (QW64:P)

#iRawInput  := "AI_Input".IW64:P;     // 16-bit peripheral input, bypasses PII
#iScaled    := SCALE_CONVERT(IN := #iRawInput,  // normalize 0..27648 to 0.0..100.0 percent
                             IOMAX := 27648.0,
                             IOMIN := 0,
                             OUTMAX := 100.0,
                             OUTMIN := 0.0);

#iRawOutput := REAL_TO_INT(#iScaled * 276.48);  // scale back to 0..27648

"AO_Output".QW64:P := INT_TO_WORD(#iRawOutput); // direct peripheral write, bypasses PIQ

Insert the OB30 into the project (Project tree > CPU > Program blocks > Add new block > Organization block > Cyclic interrupt). Set its cycle time in OB30 properties to 1.000 ms. Set the phase offset to distribute CPU load.

For the S7-1200, OB200 is also available (1 ms cyclic interrupt) on newer firmware (V4.4+). For the S7-1500, OB30-OB38 each support a different priority and configurable cycle time. Reference: S7-1500 Motion Control Function Manual (entry ID 109751825) discusses OB30+ priorities.

Step 3 - Disable Output Smoothing on the AO Channel

1. Select the analog output module in Devices & Networks.
2. For each used channel, open Properties > Outputs > Smoothing and set to None.
3. Set Output type to Voltage (0-10 V) or Current (4-20 mA) as required.
4. Set Diagnostics for wire break / short circuit as appropriate.

Step 4 - Verify Scan and Execution Order

If the AO write must occur in the same cycle as the AI read to minimize jitter, place both instructions in the same OB30. If they are in different OBs, the worst-case additional latency is one OB1 cycle (typically 1-5 ms).

Alternative: Hardware Bypass (Zero-Latency Path)

If the application is a pure signal retransmission (no PLC-side decision-making required), the most reliable approach is to wire the analog source directly to the receiving device in parallel with the PLC input. The PLC only monitors; the live signal flows through with zero PLC-introduced latency. This is the most field-proven solution for instrumentation loops where the PLC is used for logging, not control.

Implementation notes:

• Use a high-impedance voltage follower (op-amp buffer, e.g., TL072 or OPA2188) if the source cannot drive two loads without loading error.
• For current loops (4-20 mA), insert a 250 Ω precision resistor at the PLC input to convert to 1-5 V.
• Add TVS diodes and RC filtering at the PLC terminals for noise immunity, accepting that this reintroduces a small filter delay.

Quantitative Verification at 2.5 Hz

With hardware input filter set to None, OB30 at 1 ms, direct peripheral I/O, and output smoothing disabled, the expected total end-to-end latency on an S7-1214C + SM 1231 AI4 + SM 1232 AO2 system is approximately:

Phase shift at 2.5 Hz: φ = 360° · f · t = 360 · 2.5 · 0.0013 = 1.17°. This is essentially transparent on an oscilloscope and satisfies most retransmission requirements.

Verification Procedure

1. Inject a 2.5 Hz, 0-10 V sinus from a calibrated function generator into the configured AI channel.
2. Connect CH1 of an oscilloscope to the AI terminal block and CH2 to the AO terminal block.
3. Trigger on CH1 and measure the time difference between corresponding zero-crossings of the input and the output signal.
4. Compute phase shift: φ = (Δt / T) · 360°. For a 2.5 Hz signal, T = 400 ms; 1 ms delay = 0.9°.
5. Confirm visually that the output sinus amplitude and DC offset match the input within 1%.
6. If the delay still exceeds 2 ms, return to Step 1 and re-verify the filter configuration was actually downloaded to the CPU (offline/online compare in TIA Portal).

Troubleshooting Matrix

Edge Cases and Field Notes

• Firmware dependency: Direct peripheral access with :P on S7-1200 is fully supported from firmware V4.0. CPUs older than V3.0 should be upgraded before applying this technique.
• Isochronous mode: For sub-millisecond deterministic latency, configure the PROFINET IO with IRT (Isochronous Real Time) and assign the OB to a servo / isochronous OB. This is documented in SIMATIC S7-1500 Motion Control (entry ID 109751825).
• Watchdog: OB30 at 1 ms leaves only ~0.7 ms of CPU margin on an S7-1214C. If the program is heavy, increase to 2 ms or split the logic between two cyclic OBs of different priorities.
• Multiple channels: When reading more than 2 AI channels in a 1 ms OB, total conversion time may exceed the cycle. Either use a high-speed SM (e.g., SM 1231 HS) or sequence the channels in two OBs offset by 500 µs.
• Output slew rate: Some SM 1232 variants have a software slew-rate limiter that can be disabled in the device configuration. Verify by checking the output rise time on a step input.

Standards and Reference Material

• IEC 61131-2:2014 - Programmable controllers, Part 2: Equipment requirements and tests. Defines analog I/O accuracy classes and test conditions.
• IEC 61784-1 - Industrial communication networks, profiles Part 1: Fieldbus profiles. Relevant when the I/O is distributed over PROFINET.
• NE 043 (NAMUR Recommendation NE 043) - Standardization of the signal level for the failure information of digital transmitters. Useful when signal retransmission is part of a safety loop.

Quick-Reference Configuration Summary