Resolving MPI Address Conflicts on Siemens S7-300 CPU 317 2DP

Problem Description

When bringing up a minimal two-CPU MPI (Multi-Point Interface) lab network built around two SIMATIC S7-300 CPU 317 2DP stations and a programming PC equipped with the Siemens USB PC Adapter (catalog number 6ES7972-0CB20-0XA0, also designated PC Adapter USB A2), the following failure mode is reported during initial commissioning:

• STEP 7 / SIMATIC Manager Display Accessible Nodes returns only one node, and that node always appears with MPI = 2, regardless of which physical PLC is powered.
• A Download to Target System attempt targeting the second station (SIMATIC 300(2)) terminates with an error dialog, typically The online connection to the target station cannot be established or Target station not found / wrong MPI address.
• Network Detection under Set PG/PC Interface succeeds and shows the MPI bus, indicating that the cable itself and the bus physical layer are functionally intact.
• Behavior is identical whether the PC adapter is configured as the only bus master or whether it is set as a non-active participant.

This is the classic duplicate MPI address symptom, aggravated by the fact that every factory-fresh S7-300 / S7-400 CPU ships with MPI address 2 as its default value. When two such CPUs are placed on a common MPI segment without prior commissioning, they both attempt to claim address 2 simultaneously, the token arbitration resolves to one winner, and STEP 7 only ever sees the surviving station. Refer to the S7-300 Automation System Manual (Siemens entry ID 12996906) and the S7-300 CPU 31xC and CPU 31x Mounting / Operating Instructions (entry ID 8859629) for the canonical bus-parameter defaults.

Affected Hardware and Firmware

Root Cause Analysis

The MPI bus is a token-passing, RS-485-based fieldbus that supports up to 32 stations on a single segment when no repeaters are used, with each station occupying one address in the range 0 through 31. Address 0 is conventionally reserved for the PG/PC (the programming device), and addresses 1 through 31 are available for PLCs, HMIs, drives, and other active or passive participants. Two fundamental rules govern the bus, and both must hold at all times:

1. Address uniqueness. No two stations may share the same MPI / PROFIBUS address on the same segment. The active station list (GAP list) maintained by the token master can contain only one entry per address, and the PROFIBUS layer-2 FSM rejects duplicate FDL_Request requests with the same Source Address Service Access Point (SAP).
2. Single token at a time. MPI permits multiple active stations (masters), but only one can hold the token at any instant. Address collisions cause the duplicate to drop off the bus silently rather than produce a hard fault; from the operator's perspective, the second station simply never appears in Accessible Nodes.

When two brand-new CPU 317 2DP units are installed on the same PROFIBUS/MPI cable and energized for the first time, both attempt to log in at address 2. The token master (the PC adapter in this case, which by default is address 0) polls the bus, and the first responder wins the address slot. The second CPU's repeated attempts to register are rejected because address 2 is already taken. STEP 7 therefore enumerates only one online node, regardless of which CPU's PROFIBUS connector is unplugged to "test" the other. This is why unplugging CPU 1 and powering CPU 2 still yields a single station at address 2 — both CPUs are physically identical and report the same default address to the master.

The reason both CPUs initially refuse a download of HW Config is the same: STEP 7 communicates with the bus master using the configured target MPI address from the project. If the project says "address 3" but the physical CPU still believes it is address 2 (factory default), the project-level download request is misrouted, the master times out, and the dialog reports Target station not found. The fix is therefore not a cable change, a driver reinstall, or a terminating-resistor adjustment — it is a per-CPU commissioning sequence that must occur before the two stations are placed on the same segment.

Default MPI Address Behavior on Siemens CPUs

Every S7-300 / S7-400 / C7 / ET 200S CPU is shipped from the factory with the parameters in the table below. Verify against the S7-300 Module Data manual (entry ID 8859629) for any specific hardware release.

The MPI address is held in non-volatile memory inside the CPU (System Data SDB 0 and SDB 1000). It is only ever changed by one of three mechanisms:

1. A successful download of Hardware Configuration from STEP 7 / SIMATIC Manager (or TIA Portal) that includes the new address. This writes a new SDB and triggers a CPU restart.
2. Manual editing via the CPU's hardware DIP switch (where fitted) on S7-300 / S7-400 modules. A non-zero switch position overrides any project value on next power-up.
3. A memory-reset (MRES) operation — but MRES does not reset the MPI address; it only clears the user program, the retentive M/DB/T/C areas, and the diagnostic buffer. The communication SDBs are preserved.

Consequently, two out-of-the-box CPUs that have never received a project download will both report address 2 forever until individually commissioned. This is the single most common cause of the I can only see one CPU on MPI symptom and is documented explicitly in the S7-300 CPU 31xC and CPU 31x Mounting / Operating Instructions.

Pre-Commissioning Checklist

Before powering any of the CPUs, work through the following checklist. Each item is a separate potential failure source that must be eliminated before continuing to the resolution procedure.

Step-by-Step Resolution Procedure

The fix is to commission each CPU individually, on the bench, against the PC only, until each holds the MPI address expected by the project. Then reconnect the segment. The procedure below assumes project addresses 2 and 3; substitute the actual addresses of your project.

Step 1 — Connect the First CPU Only

1. Power the first CPU 317 2DP (designated SIMATIC 300(1)). Leave the second CPU powered off, or physically disconnected from the bus.
2. Connect the USB PC Adapter (6ES7972-0CB20-0XA0) directly to the first CPU's MPI/PROFIBUS connector. The single connector at the CPU end must have its terminating resistor ON.
3. Start SIMATIC Manager and open the project SIMATIC 300(1).
4. From the menu, select Options → Set PG/PC Interface, choose PC Adapter (MPI), and confirm the local address is 0 and the bus transmission rate is 187.5 kbit/s.
5. In HW Config, open CPU → Properties → Interface → MPI/DP and verify the address is 2.
6. Compile and download HW Config (Station → Save and Compile, then PLC → Download to Target System). STEP 7 prompts: Do you want to load the system data? — click Yes.
7. When prompted for the target station, ensure Accessible Nodes lists one node at MPI = 2. Select it and click OK.
8. After the download, the CPU is restarted. Verify with PLC → Accessible Nodes that the station is visible at address 2 and that the diagnostic buffer is clean (no "Parameter error" or "Bus fault" entries).

Step 2 — Connect the Second CPU Individually

1. Leave the first CPU powered but disconnect its MPI cable. Power the second CPU 317 2DP (SIMATIC 300(2)).
2. Connect the USB PC Adapter directly to the second CPU only. Its terminator must be ON.
3. Open project SIMATIC 300(2). In HW Config set the CPU's MPI address to 3 (this is the project's design value, not the factory value).
4. Compile and download HW Config. SIMATIC Manager displays a target-selection dialog. The online scan only finds one node at address 2 (because the physical CPU still defaults to address 2). Choose "Show All" or manually select MPI = 2 as the target — this is correct, because the new CPU has not yet received a download and still defaults to address 2.
5. Confirm the download. After the system data is written, the CPU restarts with the new MPI address (3).
6. Verify with PLC → Accessible Nodes that the second CPU now appears at address 3.
7. Repeat the verification: Module Information → Diagnostic Buffer should show Restart (cold start) entries with no fault codes.

Step 3 — Reconnect the Two-CPU MPI Segment

1. Power both CPUs. Both should now hold their unique MPI addresses (CPU1 = 2, CPU2 = 3).
2. Connect the bus as a three-node MPI segment: CPU1 PROFIBUS connector → cable → CPU2 PROFIBUS connector → PG tap via the third connector with the PG socket.
3. Verify termination: ON on the PROFIBUS connector at CPU1 (one end of the cable run) and ON on the PROFIBUS connector at the PG tap (other end). The middle connector, if any, must have the resistor OFF.
4. On the PG, set PC Adapter address to 0 (reserved for the programming device).
5. Run PLC → Accessible Nodes. STEP 7 should now show three entries: address 0 (PG itself), address 2 (CPU1), address 3 (CPU2).
6. To download to a specific CPU, use the project's Download to Target System with the target CPU preselected in HW Config. STEP 7 routes the connection to the correct MPI address automatically; the dialog will display Target station MPI = 2 (or 3) reached.

Topology and Termination Resistor Rules

The PROFIBUS connector family 6ES7972-0B.12-0XA0 incorporates a switchable terminating resistor network (typically 220 Ω pull-up / pull-down plus 390 Ω series, for a 150 Ω differential match). Mis-termination causes symptoms that are easy to confuse with address conflicts:

For a 3-node segment (PG + 2 CPUs) the topology must be strictly linear, with the PG tap at one end:

Downloading Hardware Configuration to Each Station

The Download to Target System dialog in SIMATIC Manager is the canonical mechanism to assign an MPI address. When the dialog opens, STEP 7 enumerates all reachable nodes and presents them by address. For each CPU that has not yet been commissioned, the address displayed is the CPU's current value (factory default 2), not the project's target value. The operator must therefore accept the current address as the target during the first download; the project value takes effect only after the SDB write completes and the CPU restarts.

For CPU 317 2DP, the HW Config download performs the following operations in order:

1. Negotiates MPI bus parameters with the target (slot time, max retry, min slave interval, quiet time).
2. Writes SDB 0 (system configuration) and SDB 1000 (MPI interface configuration) into the CPU's load memory.
3. Triggers a restart (warm or cold, depending on the SDB contents).
4. Re-connects at the new MPI address.

If the download fails at step 2 with SDB write error, the most common cause is a bus-parameter mismatch (e.g., the CPU was previously configured for 1.5 Mbit/s and the project now specifies 187.5 kbit/s). Resolve by lowering the project's bus parameters to match the CPU's current ones, downloading, then raising the rate in a second download.

Global Data Configuration for MPI

Once the two stations are individually commissioned and the segment is reconnected, the simplest mechanism for inter-CPU data exchange is Global Data. Configure it under Options → Define Global Data in SIMATIC Manager. A typical GD circle uses:

• One sender and one (or more) receivers per line. Each GD line in the GD table defines one producer-consumer pair.
• Cyclic scan rate of 1 to 22 (multiples of the CPU's OB1 cycle, typically 8). The GD scan rate sets how many OB1 cycles elapse between transmissions.
• Send/receive areas defined as DBs (recommended for typed access), M flags, or I/Q areas.

The GD table is compiled and downloaded like any other component (PLC → Download). After commissioning, verify circulation with PLC → Monitor/Modify or with the GD diagnostic view (Options → Define Global Data → View → GD Status). A common fault is a GD packet length exceeding the CPU's GD limit (CPU 317 2DP supports up to 32 GD lines, max 22 bytes per line).

Alternative: SFC67 / SFC68 / SFC69 (X_GET, X_PUT, X_ABORT)

For point-to-point data exchange that requires more structure than Global Data provides, the CPU 317 2DP supports the S7 communication via SFCs. On MPI, the most useful calls are:

Calls are made against a connection configured in Connections (NetPro) and require both ends to have matching connection IDs. Over MPI, the connection type is "S7 Connection" with a partner address equal to the remote CPU's MPI address. The active end initiates with a positive REQ pulse; the partner CPU does not require any code to handle the read because the data lands in a configured receive area.

LED Diagnostics on the CPU 317 2DP

The CPU 317 2DP front panel exposes six diagnostic LEDs. Map them to bus-related symptoms as follows:

A duplicate address condition produces no hard LED indication on either CPU; both CPUs typically boot to RUN (or STOP, depending on project) without any red light. This is intentional behavior: PROFIBUS resolves address collisions silently at layer 2. The only operator-visible symptom is the inability to enumerate the loser in STEP 7.

Bus Timing and Token Rotation Reference

MPI at 187.5 kbit/s uses an 11-bit character (1 start + 8 data + 1 parity + 1 stop), so the maximum character rate is approximately:

f_char = 187_500 / 11 ≈ 17_045 characters/s
t_char ≈ 58.7 µs per character

A typical token-pass cycle on a 3-node MPI segment (1 PG, 2 CPUs) with active participation from the PG completes in tens of milliseconds. The exact token-rotation time depends on the bus parameters (slot time, max retry, idle time, GAP rotation) which STEP 7 negotiates automatically. Engineers commissioning closed-loop communication should measure the token rotation by counting OB1 cycles over a fixed interval in a free-running counter; values well below 100 ms indicate a healthy bus. Reference the PROFIBUS standard IEC 61158 / IEC 61784 for layer-2 timing definitions; do not assume specific Siemens-published default values without verifying against the active project's bus parameters.

Common Mistakes and Field-Proven Caveats

1. Plugging both CPUs in before commissioning. This is the root cause in 90 % of "only one CPU visible" reports. Always commission each CPU against the PG alone first.
2. Forgetting that the second CPU defaults to address 2. When STEP 7 asks for the target, the operator instinctively selects "the one I want to address" (address 3 from the project) and gets "station not found". The correct answer is the address the CPU currently holds, which is 2.
3. Using the wrong MPI rate. The default for S7-300 is 187.5 kbit/s. If a previous project left the CPU at 1.5 Mbit/s, downloads at 187.5 kbit/s will fail. Lower the project's rate, download, then raise.
4. Leaving the terminating resistor ON on the middle connector. This is the second most common reason for an unstable three-node segment. The rule is simple: ON at exactly two physical ends, OFF everywhere else.
5. Setting the PC adapter to a non-zero address. The PG must be address 0. If the operator sets address 1 (or anything else), the adapter joins the active station list and may participate in token arbitration unexpectedly.
6. Re-inserting a CPU after MRES. MRES clears the user program and retentive areas but does not clear the MPI address. After MRES, the CPU still holds whatever address the project assigned at the last download.
7. Mixing S7-300 and S7-400 on the same MPI segment. Possible, but bus parameters must be aligned. S7-400 may default to 19.2 kbit/s while S7-300 defaults to 187.5 kbit/s; the master sets the rate, and a slave that cannot follow will not appear.

Verification Procedure

After completing the steps above, run the following verification sequence to confirm that the network is healthy:

1. Power both CPUs. Confirm both green RUN LEDs (or yellow STOP if no user program yet) and no red SF/BF LEDs.
2. Open PLC → Accessible Nodes in SIMATIC Manager. Expect three entries: address 0 (PG), address 2 (CPU1), address 3 (CPU2).
3. Open Module Information → Diagnostic Buffer on each CPU. Expect a clean restart event with no "Parameter error", "Bus fault", or "Duplicate station" entries.
4. Open PLC → Monitor/Modify on each CPU and toggle a flag. Confirm that the value reads back correctly across the PC adapter.
5. If Global Data is configured, open Options → Define Global Data → GD Status and verify that each GD line shows Transmitting / Receiving with no error counters incrementing.
6. Re-seat one PROFIBUS connector mid-run (briefly disconnect and reconnect). The bus should self-recover within one or two token rotations without a CPU restart.

Troubleshooting Matrix

Frequently Asked Questions