Resolving PWM Phase Mismatch Between Two S7-1200 Pulse Channels

Problem Overview: Two PWMs on the Same CPU 1214 Drift Out of Phase

The CPU 1214 exposes multiple hardware pulse generators, each implemented as an independent timer tied to a digital output. When an engineer writes the same duty cycle to two PWM channels and verifies with an oscilloscope, the two square waves almost always show a small phase offset. The waveforms are identical in frequency and duty cycle, but the rising edges do not coincide. For motion synchronization, parallel power-converter stages, dual solenoid drive, or LED dimming applications, this phase offset is unacceptable.

The root cause is rarely a hardware defect. The PWM blocks themselves are driven by on-chip timers and run independently of OB1. The phase mismatch is introduced by the way the program updates the duty cycle: when the user program writes CTRL_PWM outputs at different points in the scan, or uses immediate-write bit syntax :P, the two channels reload their compare registers at slightly different times and the rising edges separate.

This reference walks through the exact configuration steps in TIA Portal V14 SP1 and later, the program-side update pattern that locks the two channels together, and the verification procedure that confirms zero phase error with a two-channel scope.

Hardware Architecture: Pulse Generators Inside the CPU 1214

The S7-1200 CPU 1214 contains a fixed number of high-speed pulse generators that can be configured as either PWM or PTO. These generators are tied to specific transistor outputs and run from dedicated hardware timers. Because the timers are independent, no two PWM channels are inherently phase-locked at power-up: each generator starts counting from zero the moment its first pulse train is enabled.

Each pulse generator is bound to one digital output at configuration time. The mapping is established in the device configuration, not in the program. Once the binding is fixed, the output cannot be used as a normal digital output until the pulse generator is disabled.

Root Cause: Why Two PWM Channels Show Phase Offset

Three distinct mechanisms produce phase offset between two PWM channels on the same CPU 1214. They are independent and can stack.

1. Independent counter reset. Each pulse generator has its own period counter. When CTRL_PWM is called for channel 1, channel 1's counter starts from zero. When the call is made for channel 2 a few microseconds later, channel 2's counter starts from zero. The two counters therefore run from a slightly offset origin.
2. Asynchronous duty-cycle reload. PWM hardware typically loads a new duty cycle at the end of the current period. If channel 1's duty cycle is updated at scan cycle time T and channel 2's duty cycle is updated at T + dt, the two compare registers are loaded in different periods and the rising edges drift apart by dt.
3. Immediate-write bit :P writes. Using the immediate-write bit forces the CPU to commit a value outside the normal process image update. When applied to one PWM control tag and not the other, it inserts a deterministic offset between the two reload events. The user's project is doing exactly this if the two CTRL_PWM blocks are scattered across different networks or different OBs.

The first mechanism is unavoidable in hardware and is the source of the "initial" offset you observe on a cold start. The second and third mechanisms are programming patterns and can be eliminated.

Prerequisites

• SIMATIC S7-1200 CPU 1214C with transistor outputs (DC/DC/DC variant recommended).
• TIA Portal V14 SP1 or later. The configuration procedure is identical from V14 through V18.
• Firmware 4.2 or later on the CPU. Earlier firmware restricts PWM to a single channel per output pair.
• Two available transistor outputs (default Q0.0 and Q0.1).
• Two-channel oscilloscope or logic analyzer with bandwidth at least 10x the PWM frequency.
• The Siemens S7-1200 Pulse Generator (PTO/PWM) Configuration Manual open for reference.

Step-by-Step Configuration of Two Synchronized PWM Channels

1. Open the project in TIA Portal and expand Devices & Networks.
2. Select the CPU 1214 and open Device Configuration.
3. In the device view, select Pulse Generator (PTO/PWM) from the Properties pane. A list of pulse channels appears. Enable the first two channels (PWM1 and PWM2).
4. For each enabled channel, set the mode to PWM. Assign channel 1 to output Q0.0 and channel 2 to Q0.1. The output assignment is made from the drop-down next to the channel name.
5. Set the base frequency and the minimum pulse width. For a 1 kHz, 50% duty-cycle square wave on both channels, use:

   Parameter	PWM1	PWM2
   Output	Q0.0	Q0.1
   Time base	Milliseconds	Milliseconds
   Pulse duration format	Percent	Percent
   Cycle time	1 ms	1 ms
   Initial pulse width	50%	50%
   Hardware interrupt	Disabled	Disabled

6. Compile the hardware configuration and download to the CPU. The two outputs are now reserved as PWM channels and cannot be driven as normal digital outputs.

For the official configuration procedure refer to Configuring a pulse channel for PWM or PTO.

Programmatic Synchronization: One Block, One Scan, One Update

The configuration alone is not sufficient. The two channels must be started and updated from the same execution context so that the reload of the duty cycle happens within a single CPU scan. The pattern below uses a single ladder network to drive both CTRL_PWM instances simultaneously.

Ladder logic (TIA Portal, OB1):

Network 1: Synchronized PWM start/stop and duty update
|--[ M0.0 ]--[ CTRL_PWM_DB1 ]--( ENO )--|
|                                       |
|--[ M0.0 ]--[ CTRL_PWM_DB2 ]--( ENO )--|

Network 2: Single-source duty cycle distribution
|--[ MW10 ]--[ MOVE ]--[ DB1.DutyCycle ]--|
|--[ MW10 ]--[ MOVE ]--[ DB2.DutyCycle ]--|

The same MW10 source feeds both MOVE blocks. Both writes commit in the same OB1 scan. Because the underlying hardware loads the new compare value at the next period boundary, both PWMs reload on the same period boundary and the rising edges remain aligned.

If the duty cycle is computed in a function block, do not call CTRL_PWM twice with different instance DBs in different network branches. Both CTRL_PWM instances must execute in the same OB scan, in adjacent networks, and both DB1.DutyCycle and DB2.DutyCycle must be written from the same source tag before either block executes.

Correct Use of CTRL_PWM for Phase-Locked Channels

The CTRL_PWM extended instruction has the following pinout:

The duty cycle itself is not a pin of CTRL_PWM. It is written to the instance data block tag <DB>.DutyCycle as a normalized value. When the time base is Percent, write a value from 0 to 100 (REAL format). When the time base is Milliseconds or Microseconds, write the absolute on-time.

To synchronize two PWMs at start-up:

1. Disable both PWMs (ENABLE = FALSE).
2. Write the duty cycle to both instance DBs in the same network.
3. Set ENABLE = TRUE on both CTRL_PWM instances in the same network, on the same scan.

If the two ENABLE bits are set in different scans, the second channel starts one scan later than the first and its counter is offset by one period's worth of CPU time.

Verification with a Two-Channel Oscilloscope

Apply the following verification procedure before declaring the PWMs synchronized.

1. Connect channel 1 of the scope to Q0.0 and channel 2 to Q0.1. Use identical probes and ground leads of equal length to avoid skew from the probes themselves.
2. Set the scope to 2 ms/div with a 1 kHz PWM so at least three periods are visible on screen.
3. Trigger on channel 1, rising edge.
4. Measure the time between channel 1 rising edge and channel 2 rising edge. A synchronized pair shows delta-t < 50 ns (the jitter floor of the two timer domains).
5. Change the duty cycle from 25% to 75% in a single scan and confirm both channels change on the same period boundary.
6. Power-cycle the CPU. Within 200 ms of restart, both PWMs must be in phase. If they drift after a power cycle, the start sequence is being driven from two different sources.

Persistent offset of more than one period indicates that the two CTRL_PWM blocks are being called in different OBs or at different priorities. Move both calls into OB1.

Edge Cases and Field-Proven Caveats

Troubleshooting Matrix

Commissioning Checklist

• CPU 1214 firmware 4.2 or later confirmed in online & diagnostic view.
• Both pulse generators configured as PWM (not PTO) with identical cycle time.
• Outputs assigned to two distinct transistor outputs.
• Single source tag for duty cycle; both DBs updated in one network.
• No :P immediate-write on any PWM control tag.
• No HSC, PTO, or frequency-measurement function conflicting on either output.
• Oscilloscope verification performed with delta-t below the timer jitter floor.
• Power-cycle test passed with no post-restart drift.

FAQ