1. Problem Summary
The S7-1200 PID_Compact and PID_3Step technology objects on a CPU 1214 (firmware V2.2) running TIA Portal V11 SP2 Update 2 exhibit a fault where writing the value 3 (automatic) to the technology DB's Retain.Mode / mode input variable fails to bring the controller to a running state. The State output of the instance DB reads 0 (inactive), the s (actuator) output remains frozen, and the ErrorBits status word stays at 16#0000, providing no diagnostic code. A subsequent Reset toggle on the block has no effect. The PID_3Step block behaves identically. The fault can occur after a CPU STOP/RUN transition, after a power cycle, or during cyclic interrupt handling if mode changes are issued faster than the assigned OB cycle time.
This is a firmware-level defect in the PID technology object runtime; Siemens Germany confirmed the bug and forwarded it to the development team after reproducing the symptom in a controlled environment.
2. Affected Hardware and Software
| Component | Tested Version | Status |
|---|---|---|
| CPU | SIMATIC S7-1214C DC/DC/DC | Affected |
| CPU firmware | V2.2 | Affected (defect reproduced by Siemens) |
| CPU firmware | V4.x and later | Most mode-transition issues resolved |
| Engineering | TIA Portal V11 SP2 Update 2 | Affected |
| Engineering | TIA Portal V13 / V14 / V15.1 | Recommended for greenfield |
| Technology objects | PID_Compact V1.x, PID_3Step V1.x | Affected |
| OB used | Cyclic interrupt OB (OB30–OB38) | Reproduces timing variant |
Reference: S7-1200 Programmable Controller System Manual (entry ID 91696622) and the PID Control with S7-1200/1500 application example (entry ID 109478121).
3. PID_Compact / PID_3Step Variable Reference
The PID_Compact instance DB is the I/O interface of the technology object. The table below lists the fields that participate in the symptom described in this article. Field names use the exact tag spelling from the generated DB.
| Tag | Direction | Data type | Meaning / Codes |
|---|---|---|---|
| Mode | Input | INT | 0 = inactive, 1 = inactive (retain output), 2 = pretuning, 3 = automatic, 4 = manual |
| Retain.Mode | Retain | INT | Mirror of the active mode stored in retentive memory; written by the block at the end of each cycle |
| State | Output | INT | 0 = inactive, 1 = initialization, 2 = manual, 3 = automatic, 4 = alternate (warning), 5 = error |
| ErrorBits | Output | DWORD | Status bitfield; expected 16#0000 in healthy running |
| Error | Output | BOOL | TRUE if the block is in a defined error state |
| s | Output | REAL | Control output (PID_Compact) or actuator position (PID_3Step), normalized 0.0–100.0 % |
| Setpoint | Input | REAL | Engineering-unit setpoint |
| Input | Input | REAL | Engineering-unit process value |
| Input_PER | Input | INT | Analog I/O word (0–27648) |
| ManualEnable | Input | BOOL | Rising edge toggles to manual (State 2) without writing Mode=4 |
| ManualValue | Input | REAL | Manual-mode output |
| Reset | Input | BOOL | Rising edge clears ErrorBits, restarts initialization |
| sretimode | Retain | INT | Last active mode retained across power cycle (mirrors Retain.Mode in V1.x) |
| CyclicTime | Output | REAL | Measured call interval in seconds |
See the PID_Compact function block description (entry ID 108477045) for the canonical variable list, and the S7-1200 Easy Book for the technology object creation steps.
4. State Machine
The PID_Compact block implements a Moore-style state machine driven by Mode and the internal initialization sequence. The transition that fails on FW 2.2 is highlighted.
+----------+ Mode = 0 +-----------+
+------->| INACTIVE |<----------------------| INITIALIZ.|
| | State=0 | | State=1 |
| +----------+<----------+ +-----------+
| | Mode = 3 / 4
| | Mode = 0..2 |
| v |
| +-----------+ Mode=4 / ManualEnable |
| | MANUAL |<----------------+ |
+--------| State=2 | | |
^ +-----------+ | v
| | +-----------+
| Mode = 3 +--| AUTOMATIC |
+----------------------------------------| State=3 |
+-----------+
|
ErrorBits <> 0
v
+-----------+
| ERROR |
| State=5 |
+-----------+
On FW 2.2 the INACTIVE → INITIALIZATION edge triggered by writing Mode = 3 is not latched if the Retain.Mode field is not in a defined state, if the previous transition was issued within the OB cycle time, or if the technology object was started with the configuration property Enable last mode after CPU restart disabled.
5. Root Cause Analysis
Three independent root causes were identified, all of which can combine in the same project.
5.1 Mode-Transition Timing Within a Cyclic OB
PID_Compact processes its Mode input on the first call of its call point in the OB after the value changes. If two transitions are issued inside the same OB cycle (e.g. Mode := 3 on one scan, Mode := 4 on the next scan that the block has not yet serviced), the second transition overwrites the first before the block enters INITIALIZATION. The user-visible symptom is that the block sits in State = 0 with no fault bit set.
Quantitative rule: the time between consecutive writes of Mode must be greater than one OB cycle of the OB that owns the PID_Compact call point. For a PID_Compact called from OB1 with a 100 ms OB1, this is 100 ms; for OB35 (100 ms default) this is 100 ms. Siemens guidance and the symptom forum threads (entry IDs 61273 and 33957) confirm this constraint.
5.2 "Enable Last Mode After CPU Restart" Property
The technology object configuration contains a checkbox labeled Enable last mode after CPU restart in the basic settings of the PID configuration editor. If the property is unchecked and the CPU performs a STOP-to-RUN transition or power cycle, the block is initialized to Mode = 0 regardless of what the user code writes. Subsequent writes of Mode = 3 are accepted by the call interface, but the block never leaves INACTIVE.
Siemens local support confirmed this behavior and explicitly recommended that the checkbox be always set to checked in production machines where restart continuity is required. The default in the V11 SP2 configuration tool is unchecked, which is a poor choice and has been the source of most of the field complaints.
Path to the property in TIA Portal:
- Project tree → Technology objects → [PID_Compact_x].
- Open Configuration → Basic settings.
- Set Enable last mode after CPU restart = ✔.
- Compile and download the technology object to the CPU (download must be performed in STOP, or via the "Download to device" wizard with consistent software).
5.3 Retain.Mode Initialization
On first download of a brand-new technology object, the retain image of Retain.Mode is 0. The block uses Retain.Mode to determine which mode to resume in after restart. Combined with the unchecked default of 5.2, this means a fresh machine boots into State = 0 on the first power-up. After the first successful mode change the retain value updates, but only if the project is downloaded with the retain value preserved. A full download without retain-preserve resets Retain.Mode to 0.
6. Diagnostic Procedure
Use the following steps to confirm the firmware defect versus a user-code wiring error.
- Go online with TIA Portal; open the PID_Compact instance DB in the watch table.
- Force
Mode = 3from the watch table (do not write through the user program; this isolates the issue to the block). - Read
State,ErrorBits,Error, andCyclicTimefrom the same DB. - If
State = 0andErrorBits = 16#0000after a 2 s wait, the block did not process the mode change. - Toggle
Resetfrom FALSE to TRUE and back.Stateshould momentarily transition to 1 (INITIALIZATION) and then to 3. - If
Statestill reads0after the reset, the technology object is in the firmware-bug state. - Open the configuration of the PID_Compact. Read the Enable last mode after CPU restart property. If unchecked and the CPU has been power-cycled since download, this is the cause.
- Check the OB that owns the call point. Read
CyclicTimefrom the DB; if it is 0.0 s, the block has not been called once. If it is much smaller than the configured sampling time, the call is happening too often. - Open the online & diagnostic view of the technology object; the Status tab shows the internal state and any pending alarms.
Reference: S7-1200 PID commissioning FAQ (entry ID 109747167).
7. Workarounds
These workarounds are field-tested and acceptable for production use. The first two are the Siemens-recommended sequence; the third is the explicit fix.
7.1 Mode-0 Bridge Between Transitions
Always pass through Mode = 0 for at least one OB cycle when changing modes. This forces a clean INACTIVE → INITIALIZATION → AUTOMATIC/MANUAL transition and avoids the timing race described in 5.1.
// Ladder / FBD equivalent in Structured Text
IF bGoAuto THEN
IF Mode <> 0 THEN
Mode := 0; // Step 1: force INACTIVE
ELSIF tBridge.Q THEN // tBridge: TON 0.2 s, > OB cycle
Mode := 3; // Step 2: enter AUTOMATIC
END_IF;
END_IF;
The 200 ms bridge time in the example comfortably exceeds the default OB1 cycle of an S7-1214C at modest program size. The block enters State = 1 at the moment Mode is written to 3 and reaches State = 3 once the I-component is loaded.
7.2 Manual-Mode Bridge
Where 7.1 does not stabilize (more common on PID_3Step than PID_Compact), use the ManualEnable input as an intermediate step:
- Write
Mode := 4(or pulseManualEnable) — controller enters MANUAL,State = 2. - Wait at least one full OB cycle.
- Write
Mode := 0— controller enters INACTIVE. - Wait at least one full OB cycle.
- Write
Mode := 3— controller enters INITIALIZATION then AUTOMATIC,State = 3.
This sequence is more robust on the PID_3Step block because the manual-to-automatic path of the 3-step controller exercises the output transition logic that the firmware bug specifically targets.
7.3 Mode = 99 Patched Write
A user on the Siemens support thread reported that writing Mode := 99 between transitions has the same effect as writing Mode := 0 and is sometimes more reliable on the PID_3Step. Treat 99 as an undocumented "force inactive" alias and avoid relying on its semantics across firmware revisions.
7.4 Configuration Property Fix (Permanent)
Set Enable last mode after CPU restart to checked in the technology object configuration. This is the only fix that does not require user-code sequencing. Combined with 7.1, the controller becomes self-recovering across restart cycles.
8. sretimode Behavior
The sretimode retain field was added in later V1.x technology object revisions to record the active mode at the point of shutdown. Reading and writing this field can be used as a recovery step:
// On startup, after first valid OB call:
IF State = 0 AND sretimode = 3 THEN
Mode := 0;
// ... then transition sequence from 7.1
END_IF;
On FW 2.2 the field is not always populated. Upgrade the technology object to the latest V1.x revision delivered with TIA Portal V13+ and re-download to use this field reliably.
9. Firmware Update Path
The defect was forwarded to the Siemens development team and is resolved in the cumulative firmware update for the S7-1200 series.
| CPU | Firmware (recommended) | Source |
|---|---|---|
| CPU 1211C / 1212C / 1214C / 1215C / 1217C | V4.6 or later | S7-1200 firmware updates (entry ID 109751826) |
| CPU 1212FC / 1214FC / 1215FC (fail-safe) | V4.6 or later | Same page, F-variant tab |
| TIA Portal project upgrade | V16 / V17 / V18 | TIA Portal upgrade guide (entry ID 109769928) |
To perform the update on a machine already in production, use the SIMATIC Automation Tool or the online firmware update from TIA Portal in STOP. The technology object instance DB layout is forward-compatible across V1.x revisions; the user code does not need to be touched.
10. Verification Procedure
After applying any combination of workarounds, run the following acceptance test on the bench or in maintenance mode before restoring production.
- CPU in RUN, PID_Compact in
State = 0(cold start, all retains reset). - Apply the 7.4 fix and download the configuration.
- Power-cycle the CPU. After restart,
Stateshould read 0 because no mode has been written yet. - From the user code, execute the 7.1 bridge sequence targeting
Mode = 3. - Confirm
Statetransitions 0 → 1 → 3 within 1 s.ErrorBitsremains16#0000. - Force a setpoint step. The
soutput should change proportionally. Capture the trend in the trace tool to confirm closed-loop behavior. - Power-cycle the CPU a second time. After restart,
Stateshould read 3 directly because the mode-3 has been retained. - Switch to manual via
ManualEnable, wait, switch back via 7.2 bridge.Statereturns to 3 with no bump ons. - Issue a deliberate
Reset.ErrorBitsclears;Statecycles 3 → 1 → 3.
11. Cross-Platform Notes
The S7-1500 PID_Compact (V2.x) does not expose the same firmware defect. The Retain.Mode / Mode semantics and the configuration property exist on S7-1500 but the timing race in 5.1 is not reproducible on a 1500 controller. When porting an S7-1200 PID application to an S7-1500, remove the 7.1 / 7.2 sequencing code — the standard pattern of writing Mode directly is sufficient.
On the S7-1200 firmware V4.x line the technology object was split into PID_Compact V2.x and PID_3Step V2.x; the V2.x interface replaces the manual sequencing requirement with a built-in handover state machine. Projects that cannot be upgraded in place must be migrated via the TIA Portal migration tool, with re-commissioning of the PID loop in pretuning mode (Mode = 2) on the first start.
12. Field Commissioning Checklist
- ✓ PID_Compact technology object created with the correct process value scaling (Config → Process value → Scaling).
- ✓ Input_PER or Input wired; not both.
- ✓ Output
sconnected to the actuator signal or to a PWM output block. - ✓ Enable last mode after CPU restart set to checked.
- ✓ Pretuning executed successfully (State = 4, ErrBits clear,
Retain.CtrlParams.Gainnon-zero). - ✓ Fine-tuning executed if required (Mode = 3 with manual
Retain.Tuning.Heating.Setpointvalue if the controller supports it). - ✓ Mode transition sequencing in user code per 7.1 / 7.2.
- ✓ Alarm / warning handling in the HMI for
ErrorBits<> 0 andState = 5. - ✓ Tested power-cycle recovery; controller restarts in
State = 3.
Why does the PID_Compact stay in State 0 after writing Mode = 3 on an S7-1214 with firmware V2.2?
This is the documented firmware defect. The block fails to latch the mode change when the "Enable last mode after CPU restart" property is unchecked, when the call point is in a cyclic interrupt OB and the transition interval is shorter than the OB cycle, or when Retain.Mode is in an undefined state. Apply the workarounds in section 7 and update the firmware to V4.6 or later.
Where is the "Enable last mode after CPU restart" checkbox in TIA Portal?
Open the project tree, expand Technology objects, select the PID_Compact instance, then open Configuration > Basic settings. The checkbox is in the first group. The default in TIA V11 SP2 is unchecked; set it to checked for any production machine.
Does the PID_3Step block have the same defect as PID_Compact?
Yes, the same firmware bug affects PID_3Step. PID_Compact is more forgiving of the manual-mode bridge workaround; PID_3Step requires the full five-step sequence in section 7.2 or the Mode = 99 patched write.
What does ErrorBits = 16#0000 with State = 0 actually mean?
It means the block is in the dormant INACTIVE state and has not yet started its initialization sequence. The lack of an error code is by design — INACTIVE is a normal state, not an error. Treat State = 0 with ErrorBits = 0 as a "controller has not been started" condition rather than a fault.
What is the minimum firmware version that fixes this PID state issue?
Siemens Development fixed the defect in the S7-1200 cumulative firmware V4.4 and later. The current recommended firmware line is V4.6. The technology object revision V2.x (TIA Portal V13 SP1 and later) also removes the issue at the interface level.
Can I write Mode = 4 or pulse ManualEnable to bypass the issue?
ManualEnable is a one-shot toggle that does not require writing Mode = 4, and the combination is more robust than writing Mode = 3 directly. The recommended sequence is ManualEnable pulse, wait one OB cycle, Mode = 0, wait one OB cycle, Mode = 3.
Will upgrading the TIA Portal project fix the issue without a firmware change?
Only partially. TIA V13 SP1 and later ship the V2.x technology object interface, which mitigates the timing race, but the underlying V2.2 CPU firmware still contains the original defect for the V1.x interface. For a complete fix, update both the TIA Portal project and the CPU firmware.