Define the Shared-UART Architecture
A single UART can serve the MAX3232E RS-232 transceiver and THVD1450 half-duplex RS-485 transceiver because only one interface operates at a time. The supplied evidence does not include the planned schematic, so it cannot confirm pin-level correctness. The design must explicitly select the receive path, control RS-485 transmission, and prevent the unselected RS-232 transmitter from producing unintended traffic.
Galvanic isolation between the CPU and transceiver side does not isolate the RS-232 and RS-485 connectors from each other. Use isolating transceivers instead if those interfaces must also be galvanically separated.
Allocate the Isolation Channels
| Signal | Direction | Supported use |
|---|---|---|
| TXD | CPU to transceivers | Share between both transmitter paths, with gating applied to every active transmit channel. |
| DE or RTS | CPU to transceivers | Control RS-485 transmission. The UART RTS output can perform this function if the software and interface requirements permit. |
| SEL | CPU to selection logic | Select the active transceiver and force the other transmitter to its safe state. |
| RXD | Transceivers to CPU | Combine with qualified logic or select with a digital or analog multiplexer. |
Without hardware handshaking, the proposed selection scheme can use four isolated signals and a 3+1 directional isolator. RTS/CTS handshaking requires additional consideration: CTS adds a return path, while using RTS as the RS-485 transmit-enable signal prevents it from independently serving another function. Channel count therefore depends on whether SEL is generated across the isolation barrier and which handshake paths must remain independent.
Prevent Switching and Startup Contention
If only one connector has a cable attached, external bus contention is not a concern. If both connectors may remain connected, positively mute the unselected transmit path and select only its corresponding receive path. A multiplexer provides stronger separation than combining receiver outputs with an AND gate because it prevents activity from the unselected receiver from reaching the UART.
The MAX3232E has no output-disable or shutdown input in the supplied evidence. Either switch its power with a logic-level PMOS and gate its inputs so they cannot remain nonzero while unpowered, or leave it powered and force every RS-232 transmitter input to the idle state while RS-485 is selected. Logic functions such as multiplexing, AND, and OR gating can be implemented with a 74LVC1G97, subject to verification of the final polarity and truth table.
Implement and Verify the Selection Logic
- Share TXD only through logic that forces the unselected transmitter to its defined idle or disabled condition.
- Connect the RS-485 driver-enable control and decide whether its receiver remains enabled during transmission or is disabled to suppress local echo.
- Select the active receive output with a multiplexer, or qualify the two receive outputs with logic before combining them.
- For the documented gating convention, pull DE low and pull SEL and TXD high on the microcontroller side so initialization cannot inadvertently enable transmission. Reconfirm these states against the implemented SEL polarity.
- Test reset, power-up, interface changes, and simultaneous cable connection. Verify that only the selected connector transmits and that switching produces no unintended start bit or partial frame.
FAQ
Can RS-232 and RS-485 share one UART TXD pin?
Yes. TXD can feed both transceiver paths when selection logic forces the unselected transmitter to its idle or disabled state.
How many digital isolator channels are needed for a shared RS-232 and RS-485 UART?
The supported non-handshaking scheme uses four isolated signals and can fit a 3+1 directional isolator. Independent RTS/CTS or additional handshake paths require more channels or a different partition.
How do I stop the MAX3232E from transmitting when RS-485 is selected?
Switch its power with a logic-level PMOS while gating its inputs, or keep it powered and force all RS-232 transmitter inputs to their idle state. Verify the gating polarity against the final SEL truth table.