S7-1200 8AI Common-Mode Limit: 48-Cell 96V Battery Measurement

1. Overview

Measuring the voltage of every cell in a long series stack — for example, 48 lead-acid or Li-ion cells in series producing a nominal 96 V string — is a routine requirement in UPS, traction, telecom back-up, and stationary energy storage systems. An integrator proposing six 8-channel analog input modules (one per "group of eight" cells, with 6 × 8 = 48 measurement points) quickly runs into a hard electrical constraint on every Siemens SIMATIC analog input: the common-mode voltage limit.

For the SIMATIC S7-1200 SM 1231 AI family, the S7-1500 / ET 200SP AI 8xI 2-/4-wire BA (6ES7134-6GF00-0AA1), and the legacy S7-300 SM 331 AI 8 x 13 Bit (6ES7331-1KF02-0AB0), the rule is the same: (signal voltage) + (common-mode voltage) must remain inside +12 V / −12 V referred to the M terminal of the module. Stack a 48-cell 96 V battery across the inputs of a single 8AI module and the bottom of the stack sits at +96 V with respect to M, blowing the limit by an order of magnitude on the very first cell.

This reference explains the constraint, the three workable architectures (isolated signal conditioners, differential divider probes, and a 48:1 analog multiplexer), and the practical scan logic needed to make a 6 × 8 = 48 channel battery monitor from off-the-shelf Siemens AI modules.

2. The ±12 V Common-Mode Constraint

Every differential input on a Siemens SM 1231, ET 200SP AI 8xI, and SM 331 AI 8x13Bit has a finite ability to reject the voltage that is common to both input terminals with respect to the module's 0 V reference. The figure is documented in each module manual.

Stacking 48 series cells at 2 V each gives 96 V between the negative rail of cell 1 and the positive rail of cell 48. The PLC M terminal sits at a single fixed potential. Therefore the bottom of the stack is already at +96 V with respect to M before any cell voltage is even measured. No 8AI module can be wired directly across 48 cells in series — the over-voltage trips the input protection, blows the input fuse on the front-end, or simply gives a clamped, nonsensical reading while the channel slowly dies.

3. Why Direct 48-Cell Wiring Fails

Wiring cell 1 of stack A to AI0 and cell 8 of the same stack to AI7 on a single module looks plausible on paper, but produces three failure modes in the field:

1. Common-mode over-range. The most positive terminal in the stack (cell 48's positive rail) is at +96 V versus the module M. The input protection clamps and either saturates at the rail or activates the internal protection diode network.
2. Channel-to-channel ground loop. Connecting multiple cells to a non-isolated AI front-end references all 48 cells to the PLC M. If the battery itself is grounded (or floats at a different potential from the cabinet PE), large ground-loop currents flow through the analog return path.
3. Loss of isolation between strings. The user proposed 6 modules for 6 independent 48-cell strings. A non-isolated AI on each string still has its M terminal tied to cabinet ground — meaning all 6 strings are now DC-shorted through the analog M network.

None of these failures show up on the bench with a single cell. All three show up the first time the system is connected to a real 96 V string.

4. Three Workable Architectures

5. Option A — Isolated Signal Conditioners

Use a dedicated cell-voltage transmitter on every cell. Each transmitter has a high-impedance differential input across one cell and a galvanically isolated 0–10 V or 4–20 mA output. The output loop is referenced to the module M, so the PLC sees only a small, isolated signal — the 96 V common-mode sits on the input side of the transmitter and never reaches the AI front-end.

Typical wiring (per cell):

• Cell + → IN+ of transmitter
• Cell − → IN− of transmitter
• Transmitter +24 V → PSU 24 V (battery-isolated, or shared with cabinet)
• Transmitter OUT+ → AI+ (e.g., 0–10 V input range)
• Transmitter OUT− → AI− and to module M (single-point ground)

Set the AI range in the PLC hardware configuration to 0–10 V (or ±10 V if bidirectional, e.g., for a NiCd string under charge). Scale the engineering value in the user program: Volts = raw_word × 10.0 / 27648.0 / divider_ratio for the S7-1200 normalized 0–10 V range.

6. Option B — Differential Divider Probes

For a 0–5 V or 0–10 V AI, place a 10:1 or 20:1 resistor divider at each input. The cell voltage of 2.0–2.5 V (lead-acid) becomes 0.20–0.25 V at the divider tap, well within the AI input range. Critical: the divider bottom must still sit within ±12 V of the module M. Because the stack reaches 96 V at the top, this only works if every divider is also isolated (e.g., an instrumentation amp powered from an isolated DC/DC per cell) or if all 48 dividers are scanned through an analog MUX that handles the common-mode at a higher compliance node.

7. Option C — 48:1 Multiplexer with Synchronized Scan

This is the most elegant solution for a 96 V stack: a single high-voltage analog MUX (or a 16:1 stack of three MUX ICs) selects one of the 48 cell taps and presents it to a single AI channel through an instrumentation amp. The PLC uses six digital outputs (one per 8:1 MUX slice) to address which cell is being read. The MUX IC handles the common-mode voltage far above ±12 V because the MUX's analog input pins tolerate the full stack potential.

For a 96 V string, choose a MUX with input compliance to at least 120 V, e.g., a DG408-class part behind a 10 MΩ / 1 MΩ divider, or a HV analog switch module rated to ±100 V such as the ADG5401 family. Add a low-leakage buffer (e.g., AD8230 instrumentation amp) to drive the AI input.

8. Recommended Architecture for 6 × 48 = 288 Cells

For the original poster's goal of six independent 48-cell strings, a hybrid Option A + C topology works cleanly:

1. One isolated cell-voltage transmitter (e.g., Phoenix Contact MINI MCR-SL-UI-REL) per cell × 48 cells × 6 strings = 288 transmitters. Each transmitter outputs 0–10 V into a 2-wire loop.
2. Six ET 200SP AI 8xI 2-/4-wire BA modules (6ES7134-6GF00-0AA1) — one per string, 8 cells per module, 8 channels per module.
3. Each module sits on the same ET 200SP station, addressed as 6 × 8 = 48 AI words in the process image. The transmitter outputs are all referenced to the local cabinet M, so the +96 V stack potential never reaches the AI front-end.
4. Scale in the PLC: Cell_Volts = (AIW × 10.0 / 27648.0) × Calibration_Gain + Calibration_Offset. Calibration gain is the transmitter's 0–10 V → 0–3 V (or 0–5 V) factory scaling factor.

9. ET 200SP AI 8xI 2-/4-wire BA — Module Reference

The AI 8xI 2-/4-wire BA (6ES7134-6GF00-0AA1) is a basic, 8-channel, 16-bit analog input module for the ET 200SP distributed I/O system. The "BA" (Basic) variant supports voltage (±10 V, 0–10 V, ±5 V, 0–5 V, 1–5 V) and current (0/4–20 mA) modes in either 2-wire (current loop) or 4-wire (voltage source) sensor wiring.

10. SM 331 AI 8 × 13 Bit — Legacy Reference

The classic SM 331 AI 8 × 13 Bit (6ES7331-1KF02-0AB0) is the S7-300 workhorse, with the same ±12 V common-mode restriction. Its successor, the SM 331 AI 6 × TC isolated (6ES7331-7PE10-0AB0), is galvanically isolated per channel and tolerates ±50 V common-mode — a drop-in upgrade when stack voltages exceed ±12 V and you prefer to keep the MUX approach.

11. PLC Scan Logic for MUX Architecture (SCL Example)

Below is a structured-text scan loop for the multiplexer approach. The PLC increments a "cell index" 1 → 48, latches the 6-bit pattern to the MUX address lines, waits for the analog front-end to settle, then captures the AI value. Using the 6 ET 200SP modules (one per string) in parallel, the scan reads all six strings for the same cell index in one cycle, keeping the data set synchronized.

// S7-1200 / S7-1500 SCL — 48:1 mux scan
FUNCTION_BLOCK FB_CellScan
VAR
    CellIndex  : INT;          // 1..48
    SettleTime : TON;          // 50 ms settling wait
    MuxAddr    : BYTE;         // Bits 0..5 → 6-bit MUX select
    ScanEnable : BOOL;         // Start/stop from HMI
END_VAR

IF NOT ScanEnable THEN
    CellIndex := 0;
    MuxAddr   := 0;
    SettleTime(IN := FALSE);
    RETURN;
END_IF;

SettleTime(IN := TRUE, PT := T#50ms);
IF SettleTime.Q THEN
    CellIndex := CellIndex + 1;
    IF CellIndex > 48 THEN CellIndex := 1; END_IF;
    MuxAddr := INT_TO_BYTE(CellIndex - 1);
    // Write MuxAddr to digital output byte (QWx)
    "MuxAddrOut" := MuxAddr;
    // Trigger A/D conversion by toggling a one-shot done in the AI driver FB
    SettleTime(IN := FALSE);
END_IF;

Trigger the AI read in the same OB1 cycle the MUX address changes. After the 50 ms wait, read the 6 AI words (one per string) into a data block, indexed by CellIndex. Logging 288 values once every ~2.5 s (50 ms × 48 cells) is more than sufficient for battery state-of-health trending.

12. Wiring and Safety Checklist

• 96 V DC is above the 60 V DC "extra-low voltage" threshold of IEC 60364-4-41. Battery cabinets require a fused disconnect, a manual service disconnect, and clear arc-flash labelling per NFPA 70E / IEC 62619.
• Use a fuse (1 A, fast-acting) on every cell-tap lead if you tap directly to a divider network, so a tap-to-chassis short doesn't dump a 96 V arc.
• Per-channel protection: a TVS diode (e.g., SMAJ33CA) from AI+ to AI− clamps induced transients when a contactor opens.
• Common-mode choke or RC snubber (100 Ω + 100 nF) on each analog lead near the cell terminal reduces inverter-induced noise on the divider.
• Shield the analog harness; ground the shield at the cabinet end only, never at the battery end.

13. Verification and Commissioning Procedure

1. Power-up isolation check. With the battery string disconnected, power the PLC and measure with a DMM: each AI+ to module M should read < 1 mV. Any reading means the transmitter is sourcing into a shorted input.
2. Single-cell sanity. Connect cell 1 only. Verify the engineering value in the HMI matches the cell DMM reading to within 0.5 %.
3. Full-stack ramp test. Charge the string in 5 A steps from 80 V to 110 V. Watch the scaled value for cell 1 — it should remain a flat 2.0 V regardless of stack voltage. If it climbs with the stack, the divider reference is wrong and the input is following common-mode, not cell voltage.
4. Channel-to-channel offset. With all cells at rest, the spread of all 48 readings on a single string should be < 5 mV. Anything larger is resistor mismatch in the divider or AI channel offset.
5. Noise floor. With the stack at 96 V, sample 1000 readings of one channel at the configured integration time. The standard deviation should be < 0.2 mV on the 16-bit ET 200SP AI. Larger spread points to missing shielding or a ground loop.

14. Troubleshooting Matrix

15. Summary

Direct wiring of a 48-cell 96 V string to a Siemens S7-1200, ET 200SP, or S7-300 8AI module is impossible because the ±12 V common-mode limit is exceeded before the first cell is even measured. The three practical fixes are (A) an isolated transmitter per cell with a 0–10 V output, (B) a precision resistor divider feeding an isolated instrumentation amp, or (C) a 48:1 high-voltage analog multiplexer scanned by digital outputs from the PLC. For the original poster's 6 × 48 = 288 cell project, the cleanest solution is to use six ET 200SP AI 8xI 2-/4-wire BA modules (one per string) fed by 288 isolated cell-voltage transmitters, scanning all 48 channels per string in a 50 ms × 48 = 2.4 s cycle, and logging the engineering values for state-of-health trending on the HMI.